AT90S/LS2333 and AT90S/LS4433
29
Figure 31. Timer/Counter0 Block Diagram
Timer/Counter0 Control Register - TCCR0
•
Bits 7-3 - Res: Reserved bits
These bits are reserved bits in the AT90S2333/4433 and always read as zero.
•
Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, bit 2,1 and 0
The Clock Select0 bits 2,1, and 0 define the prescaling source of Timer0.
The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes are scaled directly from the CK
oscillator clock. If the external pin modes are used, for Timer/Counter0, transitions on PD4/(T0) will clock the counter even
if the pin is configured as an output. This feature can give the user SW control of the counting.
Bit
7
6
5
4
3
2
1
0
$33 ($53)
-
-
-
-
-
CS02
CS01
CS00
TCCR0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Table 9. Clock 0 Prescale Select
CS02
CS01
CS00
Description
0
0
0
Stop, Timer/Counter0 is stopped.
0
0
1
CK
0
1
0
CK / 8
0
1
1
CK / 64
1
0
0
CK / 256
1
0
1
CK / 1024
1
1
0
External Pin T0, falling edge
1
1
1
External Pin T0, rising edge
OCIE1
OCF1
T0
