AT90S/LS2333 and AT90S/LS4433
78
Notes:
1. Use t
WLWH_CE
for Chip Erase and
t
WLWH_PFB
for Programming the Fuse Bits.
2. If t
WLWH
is held longer than
t
WLRH
, no RDY/BSY pulse will be seen.
Serial Downloading
Both the Program and Data memory arrays can be programmed using the SPI bus while RESET is pulled to GND. The
serial interface consists of pins SCK, MOSI (input) and MISO (output), see Figure 66. After RESET is set low, the Program-
ming Enable instruction needs to be executed first before program/erase instructions can be executed.
Figure 66. Serial Programming and Verify
Table 33. Parallel Programming Characteristics T
A
= 25
°
C ± 10%, V
CC
=5V ± 10%
Symbol
Parameter
Min
Typ
Max
Units
V
PP
Programming Enable Voltage
11.5
12.5
V
I
PP
Programming Enable Current
250
µΑ
t
DVXH
Data and Control Setup before XTAL1 High
67
ns
t
XHXL
XTAL1 Pulse Width High
67
ns
t
XLDX
Data and Control Hold after XTAL1 Low
67
ns
t
XLWL
XTAL1 Low to WR Low
67
ns
t
BVWL
BS Valid to WR Low
67
ns
t
RHBX
BS Hold after RDY/BSY High
67
ns
t
WLWH
WR Pulse Width Low
67
ns
t
WHRL
WR High to RDY/BSY Low
20
ns
t
WLRH
WR Low to RDY/BSY High
0.5
0.7
0.9
ms
t
XLOL
XTAL1 Low to OE Low
67
ns
t
OLDV
OE Low to DATA Valid
20
ns
t
OHDZ
OE High to DATA Tristated
20
ns
t
WLWH_CE
WR Pulse Width Low for Chip Erase
5
10
15
ms
t
WLWH_PFB
WR Pulse Width Low for Programming the Fuse
Bits
1.0
1.5
1.8
ms
AT90S2333/4433
VCC
+2.7 - 6.0 V
PB5(SCK)
PB4(MISO)
PB3(MOSI)
RESET
GND
XTAL1
XTAL2
1 to 8 MHz
CLOCK IN
GND
DATA OUT
INSTR. IN
