AT90S/LS2333 and AT90S/LS4433
79
For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first exe-
cute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the Program
and EEPROM arrays into $FF.
The Program and EEPROM memory arrays have separate address spaces:
0 0 0 0 t o $ 0 3 F F / $ 0 7 F F ( A T 9 0 S 2 3 3 3 / A T 9 0 S 4 4 3 3 ) f o r P r o g r a m m e m o r y a n d $ 0 0 0 0 t o $ 0 0 7 F / $ 0 0 F F
(AT90S2333/AT90S4433) for EEPROM memory.
Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and
XTAL2.The minimum low and high periods for the serial clock (SCK) input are defined as follows:
Low:> 2 XTAL1 clock cycles
High:> 2 XTAL1 clock cycles
Serial Programming Algorithm
When writing serial data to the AT90S2333/AT90S4433, data is clocked on the rising edge of CLK.
When reading data from the AT90S2333/AT90S4433, data is clocked on the falling edge of CLK. See Figure 67, Figure 68
and Table 36 for details.
To program and verify the AT90S2333/AT90S4433 in the serial programming mode, the following sequence is recom-
mended (See four byte instruction formats in Table 35
):
1.
Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to ‘0’. If a crystal is not connected across pins
XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer can not guarantee that
SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two XTAL1 cycles
duration after SCK has been set to ‘0’.
2.
Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin
MOSI/PB3.
3.
The serial programming instructions will not work if the communication is out of syncronization. When in sync, the
second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Wheter the
echo is correct or not, all 4 bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a
positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is
no functional device connected.
4.
If a Chip Erase is performed (must be done to erase the Flash), wait t
WD_ERASE
after the instruction, give RESET a
positive pulse, and start over from Step 2. See Table 37 on page 82 for t
WD_ERASE
value.
5.
The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the
appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written.
Use Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait
t
WD_PROG
before transmitting the next instruction. In an erased device, no $FFs in the data file(s) needs to be pro-
grammed. See Table 38 on page 82 for t
WD_PROG
value.
6.
Any memory location can be verified by using the Read instruction which returns the content at the selected
address at serial output MISO/PB4.
7.
At the end of the programming session, RESET can be set high to commence normal operation.
8.
Power-off sequence (if needed):
Set XTAL1 to ‘0’ (if a crystal is not used).
Set RESET to ‘1’.
Turn V
CC
power off
