AT90S/LS2333 and AT90S/LS4433
26
MCU Control Register - MCUCR
The MCU Control Register contains control bits for general MCU functions.
•
Bits 7, 6 - Res: Reserved bit
These bits are reserved bits in the AT90S2333/4433 and always reads as zero.
•
Bit 5 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the
MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just
before the execution of the SLEEP instruction.
•
Bits 4 - SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as sleep mode.
When SM is set (one), Power Down Mode is selected as Sleep Mode. For details, refer to the paragraph “Sleep Modes”
below.
•
Bits 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 bit 1 and bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the
GIMSK is set. The level and edges on the external INT1 pin that activate the interrupt are defined in the following table:
Note:
When changing the ISC11/ISC10 bits, INT1 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register. Other-
wise an interrupt can occur when the bits are changed.
The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an
interrupt
•
Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 bit 1 and bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set.
The level and edges on the external INT0 pin that activate the interrupt are defined in the following table:
Note:
When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register. Other-
wise an interrupt can occur when the bits are changed.
Bit
7
6
5
4
3
2
1
0
$35 ($55)
-
-
SE
SM
ISC11
ISC10
ISC01
ISC00
MCUCR
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Table 7. Interrupt 1 Sense Control
ISC11
ISC10
Description
0
0
The low level of INT1 generates an interrupt request.
0
1
Any logical change on INT1 generates an interrupt request.
1
0
The falling edge of INT1 generates an interrupt request.
1
1
The rising edge of INT1 generates an interrupt request.
Table 8. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
1
The rising edge of INT0 generates an interrupt request.
