AT90S/LS2333 and AT90S/LS4433
55
Figure 48. ADC Timing Diagram, Free Run Conversion
ADC Noise Canceler Function
The ADC features a noise canceler that enables conversion during idle mode to reduce noise induced from the CPU core.
To make use of this feature, the following procedure should be used:
1.
Make sure that the ADC is enabled and is not busy converting. Single Conversion Mode must be selected and the
ADC conversion complete interrupt must be enabled. Thus:
ADEN = 1
ADSC = 0
ADFR = 0
ADIE = 1
2.
Enter idle mode. The ADC will start a conversion once the CPU has been halted.
3.
If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the MCU and exe-
cute the ADC conversion complete interrupt routine.
ADC Multiplexer Select Register - ADMUX
•
Bit 7 - Res: Reserved Bits
These bits are reserved bits in the AT90S2333/4433, and should be written to zero if accessed.
•
Bit 6 - ADCBG: ADC Bandgap Select
When this bit is set and the BOD is enabled (BODEN fuse is programmed), a fixed bandgap voltage of 1.22 ± 0.05V
replaces the normal input to the ADC. When this bit is cleared, the normal input pin (as selected by MUX2..MUX0) is
applied to the ADC.
•
Bit 5..3 - Res: Reserved Bits
These bits are reserved bits in the AT90S2333/4433, and should be written to zero if accessed.
•
Bits 2..0 - MUX2..MUX0: Analog Channel Select Bits 2-0
The value of these three bits selects which analog input 5-0 is connected to the ADC.
Bit
7
6
5
4
3
2
1
0
$07 ($27)
-
ADCBG
-
-
-
MUX2
MUX1
MUX0
ADMUX
Read/Write
R
R/W
R
R
R
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
11
12
13
MSB of result
LSB of result
ADC clock
ADSC
Hold strobe
ADIF
ADCH
ADCL
Cycle number
1
2
One Conversion
Next
Conversion
