AT90S/LS2333 and AT90S/LS4433
35
is set or cleared according to the settings of the COM11 and COM10 bits in the Timer/Counter1 Control Register TCCR1.
Refer to Table 14 for details.
Note that in the PWM mode, the 10 least significant OCR1 bits, when written, are transferred to a temporary location. They
are latched when Timer/Counter1 reaches TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the
event of an unsynchronized OCR1 write. See Figure 34 for an example.
Figure 34. Effects on Unsynchronized OCR1 Latching
During the time between the write and the latch operation, a read from OCR1 will read the contents of the temporary loca-
tion. This means that the most recently written value always will read out of OCR1.
When OCR1 contains $0000 or TOP, the output OC1 is updated to low or high on the next compare match according to the
settings of COM11 and COM10. This is shown in Table 15.
Table 13. Timer TOP Values and PWM Frequency
PWM
Resolution
Timer TOP
value
Frequency
8-bit
$00FF (255)
f
TCK1
/510
9-bit
$01FF (511)
f
TCK1
/1022
10-bit
$03FF(1023)
f
TCK1
/2046
Table 14. Compare1 Mode Select in PWM Mode
COM11
COM10
Effect on OC1
0
0
Not connected
0
1
Not connected
1
0
Cleared on compare match, up-counting. Set on compare match, down-counting
(non-inverted PWM).
1
1
Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM).
