AT90S/LS2333 and AT90S/LS4433
36
In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter changes direction at $0000. Timer Overflow
Interrupt1 operates exactly as in normal Timer/Counter mode, i.e. it is executed when TOV1 is set provided that Timer
Overflow Interrupt1 and global interrupts are enabled. This also applies to the Timer Output Compare1 flag and interrupt.
Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, the
Watchdog reset interval can be adjusted as shown in Table 6. See characterization data for typical values at other V
CC
lev-
els. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. Eight different clock cycle periods can be
selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT90S2333/4433
resets and executes from the reset vector. For timing details on the Watchdog reset, refer to page 22.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be followed when the watchdog is dis-
abled. Refer to the description of the Watchdog Timer Control Register for details.
Figure 35. Watchdog Timer
Watchdog Timer Control Register - WDTCR
•
Bits 7..5 - Res: Reserved bits
These bits are reserved bits in the AT90S2333/4433 and will always read as zero.
•
Bit 4 - WDTOE: Watch Dog Turn-Off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware
will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.
Table 15. PWM Outputs OCR = $0000 or TOP
COM11
COM10
OCR1
Output OC1
1
0
$0000
L
1
0
TOP
H
1
1
$0000
H
1
1
TOP
L
Bit
7
6
5
4
3
2
1
0
$21 ($41)
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
