AT90S/LS2333 and AT90S/LS4433
22
Figure 28. Brown-Out Reset During Operation
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this
pulse, the delay timer starts counting the Time-out period t
TOUT
. Refer to Page page 36 for details on operation of the
Watchdog.
Figure 29. Watchdog Reset During Operation
MCU Status Register - MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset.
•
Bits 7..4 - Res: Reserved Bits
These bits are reserved bits in the AT90S2333 and always read as zero.
•
Bit 3 - WDRF: Watchdog Reset Flag
This bit is set if a watchdog reset occurs. The bit is cleared by a power-on reset, or by writing a logic zero to the flag.
•
Bit 2 - BORF: Brown-Out Reset Flag
This bit is set if a brown-out reset occurs. The bit is cleared by a power-on reset, or by writing a logic zero to the flag.
•
Bit 1 - EXTRF: External Reset Flag
This bit is set if an external reset occurs. The bit is cleared by a power-on reset, or by writing a logic zero to the flag.
•
Bit 0 - PORF: Power-on Reset Flag
This bit is set if a power-on reset occurs. The bit is cleared only by writing a logic zero to the flag.
Bit
7
6
5
4
3
2
1
0
$34 ($54)
-
-
-
-
WDRF
BORF
EXTRF
PORF
MCUSR
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
See bit description
VCC
RESET
TIME-OUT
INTERNAL
RESET
V
BOT-
V
BOT+
t
TOUT
