AT90S/LS2333 and AT90S/LS4433
32
•
Bits 5..2 - Res: Reserved bits
These bits are reserved bits in the AT90S2333/4433 and always read zero.
•
Bits 1,0 - PWM11, PWM10: Pulse Width Modulator Select Bits
These bits select PWM operation of Timer/Counter1 as specified in Table 11. This mode is described on page 34.
Timer/Counter1 Control Register B - TCCR1B
•
Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs)
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is trig-
gered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one),
four successive samples are measured on the ICP - input capture pin, and all samples must be high/low according to the
input capture trigger specification in the ICES1 bit. The actual sampling frequency is the XTAL clock frequency.
•
Bit 6 - ICES1: Input Capture1 Edge Select
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on
the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred
to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.
•
Bits 5, 4 - Res: Reserved bits
These bits are reserved bits in the AT90S2333/4433 and always read zero.
•
Bit 3 - CTC1: Clear Timer/Counter1 on Compare match
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compare match. If
the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the com-
pare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescaling
higher than 1 is used for the timer. When a prescaling of 1 is used, and the compare register is set to C, the timer will count
as follows if CTC1 is set:
... | C-2 | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0, 0 | ...
In PWM mode, this bit has no effect.
•
Bits 2,1,0 - CS12, CS11, CS10: Clock Select1, bit 2,1 and 0
The Clock Select1 bits 2,1 and 0 define the prescaling source of Timer/Counter1.
Table 11. PWM Mode Select
PWM11
PWM10
Description
0
0
PWM operation of Timer/Counter1 is disabled
0
1
Timer/Counter1 is an 8-bit PWM
1
0
Timer/Counter1 is a 9-bit PWM
1
1
Timer/Counter1 is a 10-bit PWM
Bit
7
6
5
4
3
2
1
0
$2E ($4E)
ICNC1
ICES1
-
-
CTC1
CS12
CS11
CS10
TCCR1B
Read/Write
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
