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AT40K Series Configuration
Configuration is the process by which a design is loaded into an AT40K series field
programmable gate array (FPGA). AT40K series devices are SRAM based and can be
configured any number of times. The entire device or select portions can be config-
ured. Sections can be configured while others continue to operate undisturbed. Full
configuration takes only milliseconds. Partial configuration takes even less time and is
a function of design density.
Configuration data is transferred to the device in one of six modes, see Table 1. Three
dedicated input pins, M
0
, M
1
, and M
2
, determine the configuration mode. There is one
auto-configuring Master Mode, four Slave modes, and a Synchronous RAM Mode for
accessing the SRAM-based configuration memory directly from a parallel micropro-
cessor port.
Configuration States
There are four basic configuration states of operation. The first, power-on-reset,
occurs when power is first applied to the part. The FPGA initiates a complete clearing
of all internal configuration SRAM (configuration clear cycle).
The second, manual reset, occurs when the RESET pin is driven Low by the user.
Again, the FPGA initiates a configuration clear cycle.
The third is configuration download. In this state the configuration mode is active. The
FPGA accepts serial or parallel data from an outside source and configures the con-
figuration SRAM appropriately.
The fourth is idle, when there is no configuration activity.
Table 1.
AT40K Series Configuration Modes
Mode
Description
M
2
M
1
M
0
CCLK
Data
Notes
0
Master Serial
0
0
0
Output
Serial
Auto-Configuration,
Serial EEPROM
1
Slave Serial
0
0
1
Input
Serial
Microprocessor or
Serial EEPROM
7
Slave Serial
1
1
1
Input
Serial
Microprocessor or
Serial EEPROM
2
Slave Parallel
0
1
0
Input
8- or 16-bit
Word
Microprocessor or
Parallel EEPROM
6
Slave Parallel UP
1
1
0
Input
8- or 16-bit
Word
20-bit Address Out,
Parallel EPROM
4
Synchronous
RAM
1
0
0
Input
8- or 16-bit
Word
24-bit Address In,
Parallel Port of
Microprocessor
AT40K FPGA
Application
Note
Rev. 1009B–FPGA–03/02
