Artesyn BajaPPC-750, User Manual

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PCI Bus Control Signals 5-9
0002M621-15
FRAME* CYCLE FRAME. This sustained three-state line is driven by the current
master to indicate the beginning of an access, and continues to be
asserted until transaction reaches its final data phase.
GNT* GRANT. This input signal indicates that access to the bus has been
granted to a particular master. Each master has its own GNT*.
IDSEL INITIALIZATION DEVICE SELECT. This input signal acts as a chip select
during configuration read and write transactions.
INTA, B, C, D* PMC INTERRUPTS A, B, C, D. These input lines are used by the PMC
module to interrupt the baseboard. The interrupts are routed through
the interrupt controller to the CPU on BajaPPC-750.
IRDY* INITIATOR READY. This sustained three-state signal indicates that the
bus master is ready to complete the data phase of the transaction.
LOCK* LOCK. This sustained three-state signal indicates that an atomic opera-
tion may require multiple transactions to complete.
PAR PARITY. This is even parity across AD00-AD31 and C/BE0-C/BE3*. Parity
generation is required by all PCI agents. This three-state signal is stable
and valid one clock after the address phase, and one clock after the bus
master indicates that it is ready to complete the data phase (either IRDY*
or TRDY* is asserted). Once PAR is asserted, it remains valid until one
clock after the completion of the current data phase.
PERR* PARITY ERROR. This sustained three-state line is used to report parity
errors during all PCI transactions.
REQ* REQUEST. This output pin indicates to the arbiter that a particular mas-
ter wants to use the bus.
RST* RESET. The assertion of this input line brings PCI registers, sequencers,
and signals to a consistent state.
SERR* SYSTEMS ERROR. This open-collector output signal is used to report any
system error with catastrophic results.
STOP* STOP. A sustained three-state signal used by the current target to request
that the bus master stop the current transaction.
TRDY* TARGET READY. A sustained three-state signal that indicates the target’s
ability to complete the current data phase of the transaction.