Artesyn BajaPPC-750, User Manual

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6-2 BajaPPC-750: VMEbus Interface
May 2002
6.2 Universe Configuration Registers
The Tundra Universe II CA91C142 provides a single-chip, VMEbus to PCI inter-
face for the BajaPPC-750. Its registers are little-endian and occupy 4 kilobytes of
internal memory. These registers are logically divided into three groups as fol-
lows: PCI configuration space, Universe device-specific, and VMEbus control and
status.
The method of access differs according to whether it is from the PCI bus or the
VMEbus. From the PCI bus, the registers may be accessed through configuration
space or the PCI-defined base address register (PCI_BS), which resides locally at
FE80,000
16
. From the VMEbus, the registers may be accessed through the VMEbus
Register Access Image (VRAI), which occupies 4 kilobytes in A16, A24, or A32
space. Alternatively, the registers may be accessed from the VMEbus as CR/CSR
space according to the VME64 specification.
The following table summarizes the Universe control registers. Please refer to the
Universe User Manual for detailed descriptions of the control bits.
Slave Enables Slave enables are provided for each VMEbus space to which the BajaPPC-
750 responds—extended, standard, and short space. All three address
spaces are initially disabled so that the CPU can control when slave
accesses may first occur. The Artesyn monitor NVRAM configuration
parameters (see Section 10.7) can program the slave interface to negate
SYSFAIL* when ready. Also, the monitor can enable the slave image inde-
pendently.
Table 6-1. Universe Internal Register Summary
Hex Offset Mnemonic Name
000 PCI_ID PCI Configuration Space ID Register
004 PCI_CSR PCI Configuration Space Control and Status Register
008 PCI_CLASS PCI Configuration Class Register
00C PCI_MISC0 PCI Configuration Miscellaneous 0 Register
010 PCI_BS PCI Configuration Base Address Register
014 PCI_BS1 PCI Configuration Base Address Register 1
018-024 PCI Unimplemented
028-2C PCI Reserved
030 PCI Unimplemented
034-038 PCI Reserved
03C PCI_MISC1 PCI Configuration Miscellaneous 1 Register
040-0FF PCI Unimplemented
100 LSI0_CTL PCI Slave Image 0 Control
104 LSI0_BS PCI Slave Image 0 Base Address Register