Artesyn BajaPPC-750, User Manual

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PCI Bridge Configuration Registers 5-5
0002M621-15
5.3.2 PCI Status Register
The MPC106 PCI Status Register at hex offset 06
16
records status information for
PCI-related events. (See important note below regarding RMA master abort status
bit.)
SC Special cycles. Hardwired to zero (ignore SC commands).
BM Bus master. 0=PCI access disable, 1=bus master enable.
MS Memory space access response. 0=disable, 1=enable.
IOS I/O space. Hardwired to zero (no response to PCI I/O space accesses).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPE SSE RMA RTA STA DSEL DPD FBB Res. 66M Reserved
Register Map 5-2. MPC106 PCI Status
DPE Detected parity error. 1=parity error.
SSE Signalled system error. 1=SERR* asserted.
RMA Received master abort. 1=transaction terminated by master abort.
CAUTION. You might need to clear the RMA bit more than once.
After a master abort, always read the status of this bit to
verify that it cleared successfully.
RTA Received target abort. 1=transaction terminated by target abort.
STA Signalled target abort. 1=target abort issued to a PCI master.
DSEL Device select timing. Hardwired to 0B00
16
(fast select).
DPD Data parity detected. 1=parity error (while MPC106 is bus master and PCI
Command Register, bit 6, is set).
FBB Fast back-to-back capable. Hardwired to one (accept fast back-to-back
transactions).
66M 66-MHz capable. Read only indicator that MPC106 cannot operate the
PCI bus at 66 MHz.