Artesyn BajaPPC-750, User Manual

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5-8 BajaPPC-750: PMC/PCI Interface
May 2002
5.5 PCI Bus Control Signals
The following signals for the PCI interface are available on connectors J1x and
J2x. Refer to the PCI specification for detailed usage of these signals. All signals
are bi-directional unless otherwise stated.
NOTE. A sustained three-state line is driven high for one clock cycle before
float.
BNK [3:1] Rotate
Enable
These bits default to 111
2
(rotation enabled).
BNK4 Fixed
Mode Priority
These bits select the priority as follows:
00
2
selects IDE
➔
bank1
➔
bank2
➔
bank3;
01
2
selects bank1
➔
bank2
➔
bank3
➔
IDE;
10
2
selects bank2
➔
bank3
➔
IDE
➔
bank1;
11
2
selects bank3
➔
IDE
➔
bank1
➔
bank2
BNK [3:1] Fixed
Mode Priority
If no upper bits are chosen, IDEIRQ* priority is always higher than
REQ4*
ACK64*, REQ64* These output signals are used to tell a 64-bit PCI device whether to use
the 64-bit or the 32-bit data width. Since the BajaPPC-750 is a 32-bit
board, these signals are tied off to indicate the 32-bit data width.
AD00-AD31 ADDRESS and DATA bus (bits 0-31). These three-state lines are used for
both address and data handling. A bus transaction consists of an address
phase followed by one or more data phases.
BUSMODE1*-4* On the BajaPPC-750, BUSMODE2* is tied high and BUSMODE3* and
BUSMODE4* are tied low to indicate to the module that the BajaPPC-750
is a PMC baseboard. The module uses BUSMODE1* to indicate that it is
present and compatible with the BajaPPC-750.
C/BE0* -C/BE3* BUS COMMAND and BYTE ENABLES. These three-state lines have differ-
ent functions depending on the phase of a transaction. During the
address phase of a transaction these lines define the bus command. Dur-
ing a data phase the lines are used as byte enables.
CLK Clock. This input signal to PMC modules provides timing for PCI trans-
actions.
DEVSEL* DEVICE SELECT. This sustained three-state signal indicates when a
device on the bus has been selected as the target of the current access.