Artesyn BajaPPC-750, User Manual

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User Flash 4-3
0002M621-15
4.3 User Flash
The BajaPPC-750 provides 12 megabytes of User Flash. Four megabytes of 8-bit
wide flash is paged 512 kilobytes at a time to the address space at FF88,0000
16
.
This memory is paged because the address window is limited to 512 kilobytes. If
booting from User Flash, Bank 0 is addressed at FF80,0000
16
. The byte-wide Flash
Bank Select register (R/W) at FF98,0010
16
selects one of the eight User Flash pages
at a time. All the Flash Bank Select Register bits are set to zeroes at power-up.
In addition to the four megabytes of paged User Flash, the BajaPPC-750 provides
another eight megabytes of 64-bit wide flash, beginning at address FF00,0000
16
.
This memory must be accessed with 64-bit transfers from the PowerPC.
4.4 On-Card SDRAM
The BajaPPC-750 supports 32-, 64-, 128-, and 256-megabyte configurations of 64-
bit wide synchronous DRAM (SDRAM). The memory chips are 4Mx16 or 8Mx16,
3.3-V, SDRAM devices arranged in up to eight banks of four devices. (Currently,
no configurations utilize more than four banks. Revision 22 and higher boards do
not support more than four banks.) On-card RAM occupies physical addresses
from 0000,0000
16
to 0FFF,FFFF
16
.
The SDRAM is controlled by the MPC106 DRAM controller, which may be pro-
grammed for most memory sizes and speeds, various block sizes, and write pro-
tection.
In addition to the basic SDRAM control functions the MPC106 chip provides sev-
eral additional DRAM-related functions and contains the following performance
enhancing features:
• Programmable delay insertion for controlling RAS precharge time, RAS low
time, CAS setup before RAS time, CAS precharge time, CAS pulse width, CAS
access time, and address access time.
• Logic needed to control parity generation, and checking logic with functions
to clear parity errors.
7 6 5 4 3 2 1 0
reserved
bank
address
2
bank
address
1
bank
address
0
Register Map 4-1. BajaPPC-750 Flash Bank Select