Artesyn BajaPPC-750, User Manual

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10-6 BajaPPC-750: Monitor
May 2002
5. Write a “3” to the LED display. Activiate serial port 1 on the Ultra I/O control-
ler.
6. Write a “4” to the LED display. Perform a rotating bit test on the scratch regis-
ter of the UART. If an error is detected, the LED display will flash “A”
(address), “B” (data read), and “C” (data written).
7. Write a “5” to the LED display. Initialize the serial port for 9600 baud and
check for a pressed key. If a “d” key is pressed, start the debugger. If an “s” key
is pressed, skip the diagnostics,
nvopen , and configboard , and use the
default NVRAM parameters. If no key is pressed, or if any other key is pressed,
then read NVRAM parameters to determine if diagnostics should be executed
and if parity should be enabled.
8. Turn off the LED display and print the monitor version number. If memory
parity was requested, set memory to read-modify-write mode.
9. Enable the L1 instruction cache.
10. Print a test hexadecimal number. Print the memory size (read from the Board
Configuration Register).
11. Write a “7” to the LED display. Check timebase timer function. Counter/
timer test flag (Table 10-1) reports failures. If an error occurs, the debugger
starts.
12. Write an “8” to the LED display. Write and read locations 0x40000 and
0x4000004 with the data pattern 0x05050a0a and its complement. DRAM
data test flag (Table 10-1) reports failures. If a failure occurs, the monitor dis-
plays the failed address, followed by the incorrect data and the expected data;
then the debugger starts.
13. Write a “9” to the LED display. Perform a rotating bit test on all address
boundaries with parity disabled. Then initialize the address boundaries by
writing each long word with its own address. DRAM data test flag (table)
reports failures. If a failure occurs, the monitor displays the failed address, fol-
lowed by the incorrect data and the expected data, and the debugger starts.
14. Write an “A” to the LED display. If the parity SDRAMs are installed and mem-
ory parity is requested, test the ability to detect bad parity. Write a value with
even parity to address 0x4000. Then with parity generation turned off,
change the data to odd parity. Reading the value at the address should cause a
parity error. If an error occurs, the debugger starts.
15. Write a “B” to the LED display. If the parity SDRAMs are installed and mem-
ory parity is requested, enable parity checking; then write and read offset
0x40000 and 0x40004 in each memory bank with data patterns that have
opposite byte parity (i.e., 0x01030103 and 0x03010301). The DRAM data and