Artesyn BajaPPC-750, User Manual

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Serial Ports 8-11
0002M621-15
The Modem Status Register, MSR, tracks the status of the serial port device. These
bits all are reset to zero whenever the MSR is read.
PE Parity error. 1 = parity error detected. This bit is reset when read.
FE Framing error. 1 = framing error detected (no stop bit). This bit is reset
when read.
BI Break interrupt. 1 = received data was held at logic “0” for longer than a
full word transmission time. This bit is reset when the CPU reads the
LSR.
THRE Transmitter holding register empty. 0 = serial port not ready, 1 = serial
port ready for transmission
TEMT Transmitter empty. 0 = THR or TSR contains a data character, 1 = THR
and TSR are empty
FIFO_ER FIFO error. This bit is always zero, except in FIFO mode, where 1 = FIFO
error
0 1 2 3 4 5 6 7
DCTS DDSR TERI DDCD CTS DSR RI DCD
Register Map 8-6. Ultra I/O Serial Port Modem Status, MSR
DCTS Delta clear to send. 1 = nCTS changed state
DDSR Delta data set ready. 1 = nDSR changed state
TERI Trailing edge of ring indicator. 1 = nRI changed state to logic “1”
DDCD Delta data carrier detect. 1 = nDCD changed state
CTS Complement of clear to send (nCTS) input.
DSR Complement of data set ready (nDSR) input.
RI Complement of ring indicator (nRI) input.
DCD Complement of data carrier detect (nDCD) input.