9-2
BajaPPC-750: Counter/Timers
9.2.1 Period Register
The Period Register, CTPR, specifies the period to be used by the counter/timer.
The value written indicates the number of 14.31818 MHz clocks between inter-
rupts. This register can specify periods from 120 nanoseconds to 4.29 minutes.
The formula for determining the correct value is:
Value = ((desired period in nanoseconds)/69.8) – 1
or
Value = (14,318,180/frequency in Hz) – 1
This register can be read at anytime, but it can only be written when the timer is
disabled. At reset the period register is initialized to generate 10.00002-millisec-
ond interrupts.
9.2.2 Count Register
The Count Register, CTCR, returns the current contents of the counter. When the
counter is activated, it is loaded with the contents of the period register and
counts down from this value until zero is reached. Reading this register provides
the time remaining until the timer generates an interrupt.
9.2.3 Status Register
The Status Register, CTSR, is a read-only register that returns both the configura-
tion, as specified by the mode register CTMR, and the status information for the
timer. The format of this register is described in the following table.
DH0
DH1
DH2
DH3
DH4
DH5
DH6
DH7
CInPrg
Ovflow
InPend
StrStp
IntrEn
OvFlEn
CTMode
Enable
Register Map 9-1. Counter/Timer Status, CTSR
Summary of Contents for BajaPPC-750
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Page 57: ...3 12 BajaPPC 750 Central Processing Unit May 2002...
Page 77: ...5 12 BajaPPC 750 PMC PCI Interface May 2002...
Page 111: ...6 34 BajaPPC 750 VMEbus Interface May 2002...
Page 135: ...8 18 BajaPPC 750 Serial and Parallel I O May 2002...
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