Artesyn BajaPPC-750, User Manual

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Interrupt Handling 3-7
0002M621-15
3.4 Interrupt Handling
The interrupt controller on the BajaPPC-750 is a programmable logic device
(PLD) that handles seven local interrupts and receives external interrupts from
the counter/timers and PMC modules. (See Chapters 6 and 9 for additional infor-
mation.) The interrupt controller drives the 750_INT* interrupt input on the
CPU. The interrupt controller’s registers are accessible through the MPC106 ROM
interface.
When an interrupt is pending, the CPU may read a unique vector from the con-
troller at location FF9A,0060
16
or the current state of the interrupts from the
Interrupt Status Register at FF9A,0070
16
. These 32-bit registers are connected to
the most significant long word on the CPU bus.
Table 3-5. Interrupt Vector Assignments
Interrupt Source Mnemonic Priority Hex Vector
Counter/Timer 2 CT2 Highest 0000,00B8
Counter/Timer 1 CT1 0000,00B0
Ethernet ETH 0000,00A8
PMC Site 2 INTD* J2x INTD 0000,00A0
PMC Site 2 INTC* J2x INTC 0000,0098
PMC Site 2 INTB* J2x INTB 0000,0090
PMC Site 2 INTA* J2x INTA 0000,0088
PMC Site 1INTD* J1x INTD 0000,0080
PMC Site 1 NTC* J1x INTC 0000,0078
PMC Site 1INTB* J1x INTB 0000,0070
PMC Site 1INTA* J1x INTA 0000,0068
Universe output LINT7 0000,0060
Universe output LINT6 0000,0058
Universe output LINT5 0000,0050
Universe output LINT4 0000,0048
Universe output LINT3 0000,0040
Universe output LINT2 0000,0038
Universe output LINT1 0000,0030
Universe output LINT0 0000,0028
ISA bridge chip ISA INT 0000,0010
Reset switch NMI 0000,0008
None pending – Lowest 0000,0000