Artesyn BajaPPC-750, User Manual

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Basic Operation 10-7
0002M621-15
DRAM parity test flags (Table 10-1) report failures. If an error occurs, the test
attempts to determine which byte lanes failed the parity test. Afterwards, the
diagnostics continue with parity disabled.
16. Write a “C” to the LED display. Perform a rotating bit test on the first
0x40000 of memory required by the monitor. If a data error occurs, the
debugger starts. If a parity error occurs, the test displays the error and contin-
ues the test with parity disabled.
17. If the parity SDRAMs are installed and memory parity is requested, enable
parity checking; then initialize the lower 0x40000 of memory by writing each
long word with its own address. Verify the data written. The DRAM data test
flag (Table 10-1) reports failures. If a data error occurs, the monitor displays
the failed address, followed by the incorrect data and the expected data, and
the debugger starts. If a parity error occurs, the test displays the error and
continues the test with parity disabled. Note: this test is performed if memory
parity is enabled in the NVRAM parameters, even if the diagnostics are dis-
abled. To avoid erasing memory, disable both diagnostics and parity in the
NVRAM parameters.
18. Initialize at system level to set up for running compiled C code. Enable
machine checks in the MPC106 and initialize BSS. Relocate the dynamic data
section from ROM to its linked address space starting at 0x2000. Initialize the
stack pointer to 0x1FFF8.
19. If an “s” key was not pressed on the serial port, load NVRAM data into mem-
ory and configure board according to the parameters in NVRAM. If NVRAM is
invalid or the monitor detected a pressed key, load the default parameters
into memory. (See Table 10-3 for default NVRAM parameters.) In either case,
the actual NVRAM contents are left unchanged and may be edited with
nvdisplay , followed by nvupdate .
Finally, configure the serial port with the parameters that were loaded into
memory.
20. Initialize the RAM-based interrupt vector table. Change the interrupt prefix
to point to the RAM-based interrupt table at 0x00000000. Initialize the
MPC106 error registers, interrupt handler table, and timebase register.
21. Store the results of the power-up diagnostics at an offset of 0x60 in NVRAM.
To read the PASS/FAIL flags, do four byte reads from the NVRAM at 0x60,
0x61, 0x62, and 0x63. The byte at 0x60 should contain the magic number
0xa5 indicating that the device is functional and that PASS/FAIL reporting is
supported. The values for the long word when a failure occurs are listed in
Table 10-1.