Artesyn BajaPPC-750, User Manual

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Basic Operation 10-5
0002M621-15
finally, the test writes a unique address value to every 32-bit
long word to check for address mirrors.
i [0 1] Enable [1] or disable [0] the L1 instruction cache.
m Attempt to initialize the stack and monitor data, and start the
monitor without executing the powerup/reset diagnostics.
10.2 Basic Operation
The BajaPPC-750 monitor performs various configuration tasks upon power-up
or reset. This section describes the monitor operation as it relates to these specific
tasks and the memory initialization. The flowcharts beginning on page 9 illus-
trate the power-up/reset sequence (bold texts in flowcharts indicate NVRAM
parameters).
10.2.1 Power-Up/Reset Sequence
At power-up or board reset, the monitor performs hardware initialization, diag-
nostics, autoboot procedures, free memory initialization, and if necessary,
invokes the command-line editor.
Power-up sequence:
If an unexpected interrupt occurs before the console port is ready, the LED
flashes “E”, followed by the exception number. If the exception number is
“2”, then the LED displays:
“A” for machine check detected,
“B” for transfer error acknowledge detected,
“C” for data parity error, or
“D” for address parity error.
1. Initialize the MPC106 and turn off the LED display.
2. Read the Board Configuration Register to determine power-up or reset.
3. Write a “1” to the LED display. Check the decrementer function. The counter/
timer test flag (Table 10-1) reports failures. If this first step fails, the LED dis-
play flashes “1” continuously.
4. Write a “2” to the LED display. Test the PCI to ISA bridge connection with a
rotating bit test of the DMA scatter/gather register at address FE00,0420
16
. If
an error is detected, the LED display will flash “A” (address), “B” (data read),
and “C” (data written).