41978 AMD RS690M Databook 3.06
© 2008 Advanced Micro Devices, Inc.
Table of Contents-2
Proprietary
2.4 DVI/HDMI (Not Applicable to the RS690MC)
2.4.1
DVI/HDMI Data Transmission Order and Signal Mapping
................................................................................ 2-9
2.4.2
Chapter 3: Pin Descriptions and Strap Options
3.1 Pin Assignment
3.1.1
3.1.2
3.3 CPU HyperTransport™ Interface
3.4 DDR2 Side-port Memory Interface (RS690T only)
3.5.1
1 x 16 Lane Interface for External Graphics (Not Applicable to the RS690MC)
............................................... 3-9
3.5.2
A-Link Express II to Southbridge
3.5.3
4 x 1 Lane Interface for General Purpose External Devices
.............................................................................. 3-9
3.5.4
Miscellaneous PCI Express® Signals
3.9 TMDS Interface Multiplexed on the PCI Express® Graphics Lanes (Not Applicable to the RS690MC)
Chapter 4: Timing Specifications
4.1 CPU HyperTransport™ Bus Timing
4.2 HyperTransport™ Reference Clock Timing Parameters
................................................................................................... 4-1
4.3 PCI Express® Differential Clock AC Specifications
4.4 Side-port Memory Timing (RS690T Only)
4.4.1
4.4.2
4.7 Power Rail Power Up Sequence