41978 AMD RS690M Databook 3.06
© 2008 Advanced Micro Devices, Inc.
2-2
Proprietary
Host Interface
2.1
Host Interface
The RS690M is optimized to interface with the Athlon 64/Athlon 64 FX/Athlon X2/AMD Sempron/AMD Turion 64
processors, including both AM2 and S1 socket CPUs. This section presents an overview of the HyperTransport™
interface. For a detailed description of the interface, please refer to the HyperTransport I/O Link Specification from the
HyperTransport Consortium.
Figure 2-2, “Host Interface Block Diagram,”
illustrates the basic blocks of the host bus
interface of the RS690M.
Figure 2-2 Host Interface Block Diagram
The HyperTransport (HT) Interface, formerly known as the LDT (Lightning Data Transport) interface, is a high speed,
packet-based link implemented on two unidirectional buses. It is a point-to-point interface where data can flow both
upstream and downstream at the same time. The commands, addresses, and data travel in packets on the HyperTransport
link. Lengths of packets are in multiples of four bytes. The HT link consists of three parts: the physical layer (PHY), the
data link layer, and the protocol/transaction layer. The PHY is the physical interface between the RS690M and the CPU.
The data link layer includes the initialization and configuration sequences, periodic redundancy checks,
connect/disconnect sequences, and information packet flow controls. The protocol layer is responsible for maintaining
strict ordering rules defined by the HT protocol.
The RS690M HyperTransport bus interface consists of 17 unidirectional differential data/control pairs and two
differential clock pairs in each of the upstream and downstream direction. On power up, the HT link is 8 bits wide and
runs at a default speed of 200MT/s. After negotiation, carried out by the HW and SW together, the link width can be
brought up to 16 bits and the interface can run up to 2GT/s. The interface is illustrated in
Interface Signals,” on page 2-3.
The signal name and direction for each signal is shown with respect to the processor.
Please note that the signal names may be different from those used in the pin listing of the RS690M. Detailed descriptions
of the signals are given in
section 3.3, “CPU HyperTransport™ Interface‚’ on page 3-8
HT Interface to CPU (PHY)
Configuration
Registers
Root Complex
Memory Controller
LTA
LRA
SCH
Data Link Layer
Protocol/Transaction Layer
