AMD RS690M, Technical Reference Manual

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41978 AMD RS690M Databook 3.06 © 2008 Advanced Micro Devices, Inc.
3-8 Proprietary
CPU HyperTransport™ Interface
3.3 CPU HyperTransport
™
Interface
3.4 DDR2 Side-port Memory Interface (RS690T only)
Table 3-1 CPU HyperTransport™ Interface
Pin Name Type
Power
Domain
Ground
Domain
Functional Description
HT_RXCAD[15:0]P,
HT_RXCAD[15:0]N
I VDDHT VSS Receiver Command, Address, and Data Differential Pairs
HT_RXCLK[1:0]P,
HT_RXCLK[1:0]N
I VDDHT VSS
Receiver Clock Signal Differential Pair. Forwarded clock signal. Each byte of
RXCAD uses a different clock signal. Data is transferred on each clock edge.
HT_RXCTLP,
HT_RXCTLN
I VDDHT VSS
Receiver Control Differential Pair. For distinguishing control packets from data
packets.
HT_TXCAD[15:0]P,
HT_TXCAD[15:0]N
O VDDHT VSS Transmitter Command, Address, and Data Differential Pairs
HT_TXCLK[1:0]P,
HT_TXCLK[1:0]N
O VDDHT VSS
Transmitter Clock Signal Differential Pair. Each byte of TXCAD uses a different
clock signal. Data is transferred on each clock edge.
HT_TXCTLP,
HT_TXCTLN
O VDDHT VSS
Transmitter Control Differential Pair. Forwarded clock signal. For
distinguishing control packets from data packets.
HT_RXCALN Other VDDHT VSS Receiver Calibration Resistor to VDD_HT power rail.
HT_RXCALP Other VDDHT VSS Receiver Calibration Resistor to Ground
HT_TXCALP Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALN
HT_TXCALN Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALP
Table 3-2 DDR2 Side-port Memory Interface (RS690T Only)
Pin Name Type
Power
Domain
Ground
Domain Integrated
Termination
Functional Description
MEM_A[13:0] O VDD_MEM VSS None
Memory Address Bus. Provides the multiplexed row and column
addresses to the memories.
MEM_BA[2:0] O VDD_MEM VSS None Memory Bank Address
MEM_RAS# O VDD_MEM VSS None Row Address Strobe
MEM_CAS# O VDD_MEM VSS None Column Address Strobe
MEM_WE# O VDD_MEM VSS None Write Enable Strobe
MEM_CKE O VDD_MEM VSS None Clock Enable
MEM_CKP O VDD_MEM VSS None Memory Differential Positive Clock
MEM_CKN O VDD_MEM VSS None Memory Differential Negative Clock
MEM_CS# O VDD_MEM VSS None Chip Select
MEM_ODT O VDD_MEM VSS None On-die Termination
MEM_DQ[15:0] I/O VDD_MEM VSS None Memory Data Bus. Supports SSTL2 and SSTL3.
MEM_DM[1:0] I/O VDD_MEM VSS None Data masks for each byte during memory write cycles
MEM_DQS[1:0]P I/O VDD_MEM VSS None
Memory Data Strobes. These are bi-directional data strobes for
latching read/write data.
MEM_DQS[1:0]N I/O VDD_MEM VSS None Do not connect.
MEM_COMPP,
MEM_COMPN
Other VDD_MEM VSS None
Memory interface compensation pins for N and P channel
devices. Connect through resistors to VDD_MEM and ground
respectively (refer to the reference schematics for the proper
resistor values).
MEM_VREF Other – VSS None
Reference voltage. It supplies the threshold value for
distinguishing between “1” and “0” on a memory signal. Typical
value is 0.5*VDD_MEM.