© 2008 Advanced Micro Devices, Inc.
41978 AMD RS690M Databook 3.06
Proprietary
B-1
Appendix C
Revision History
Rev 0.1 (March 2006)
•
First release.
Rev 0.2 (May 2006)
•
Swopped positions of DEBUG13 and DEBUG14 for the RS690M. Affected sections: Section 3.1, “Pin Assignment,”
Section 3.14, “Debug Port Signals,” and Appendix A, “Pin Listings.”
•
Added Section 1.5.11, “DVI/HDMI (Not applicable to the RS690MC).”
•
Updated Section Section 1.5.12, “Power Management Features”: Specified that lane reduction on RS690T’s PCI-E
graphics link is not available when lane reversal is in effect.
•
Updated Section 1.8, “Part Number Legend”: Added part numbers.
•
Added Section 2.4, “DVI/HDMI (Not Applicable to the RS690MC).”
•
Updated Section 3.5.4, “Miscellaneous PCI Express® Signals”: Corrected connection for PCE_CALRP (should be
grounded through a resistor).
•
Updated Section 3.6, “Clock Interface”: Revised description of TVCLKIN.
•
Updated Section 4.4, “Side-port Memory Timing (RS690T Only)”: Added details on DLL programming for the
side-port memory interface.
•
Updated Table 4-4, “Timing Requirements for the OSCIN Pad”: Changed maximum cycle-to-cycle jitter to 300ps;
removed peak-to-peak and lone-term jitter specifications.
•
Updated Table 5-10, “RS690M/690T 465-Pin FCBGA Package Physical Dimensions”: Revised die size values (D2
and E2).
•
Updated Section 5.3.3, “Board Solder Reflow Process Recommendations”: Removed information on eutectic solder,
as it is irrelevant.
•
Updated Table 6-2, “ACPI Signal Definitions”: Removed SUS_STAT# from SB form the table.
•
Updated Table 7.4.2, “VOH/VOL Tree Activation”: Corrected instruction in step 10 to 0101 1101.
Rev0.3 (Aug 2006)
•
Added references to the RS690MC.
•
Added legal disclaimers concerning DVI and HDMI references in this book.
•
Updated Section 1.6, “Branding Diagram”: Added branding diagrams.
•
Updated Section 2.4, “DVI/HDMI (Not Applicable to the RS690MC)”: Changed section title; corrected data ordering
of DVI/HDMI.
•
Changed the way in which the TMDS interface (multiplexed on the PCI-E graphics lanes) is being referred to.
•
Updated Table 3-19, “TMDS Interface Multiplexed on the PCI-E Graphics Interface”: Corrected mapping
relationships between and PCI-E and TMDS signals.
•
Updated Section 3.11, “Miscellaneous Pins”: Added description for pulse-width modulation function of the following
pins: STRP_DATA, and TMDS_HPD; added description for DDC_DATA.
•
Updated Table 3-17, “Strap Definitions for the RS690M”: Added descriptions for two Reserved straps for the
RS690M.
•
Added Section 4.1, “CPU HyperTransport™ Bus Timing”: Referred designers to AMD specifications.
•
Updated Section 4.6, “OSCIN Timing”: Removed high and low time requirements.
•
Updated Section 4.7, “Power Rail Power Up Sequence”: Added power rail power up sequence.
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