Power Management Pins
© 2008 Advanced Micro Devices, Inc.
41978 AMD RS690M Databook 3.06
Proprietary
3-13
3.10
Power Management Pins
3.11
Miscellaneous Pins
GFX_TX5P
P2
TX4P- 2nd Link Green+
GFX_TX5N
P1
TX4M - 2nd Link Green-
GFX_TX6P
P3
TX3P - 2nd Link Blue+
GFX_TX6N
R3
TX3M - 2nd Link Blue-
Table 3-11 Power Management Pins
Pin Name
Type
Power
Domain
Ground
Domain
Functional Description
LDTSTOP#
I
VDDR3
VSS
HyperTransport Stop. Input from the Southbridge to enable and disable the
HyperTransport link during system state transitions. For systems requiring power
management. Single-ended.
ALLOW_LDTSTOP
OD
VDDR3
VSS
Output going to the Southbridge to allow LDTSTOP assertions:
1 = LDTSTOP# can be asserted
0 = LDTSTOP# has to be de-asserted
SYSRESET#
I
VDDR3
VSS
Global Hardware Reset. This signal comes from the Southbridge.
POWERGOOD I
VDDR3
VSS
Input
from the motherboard signifying that the power to the RS690M is up and
ready. Signal high means all power planes are valid. It is not observed internally
until it has been high for more than 6 consecutive REFCLK cycles. The rising edge
of this signal is deglitched. The nominal input high voltage is 3.3V.
Table 3-12 Miscellaneous Pins
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description
BMREQ#
O
VDDR3
VSS
–
This output signal to the Southbridge indicates that there is a DMA
request from a PCI Express Bus device. The signal is not used on
the RS690M platforms and should be left unconnected.
DEBUG[15:13, 10:9,
6, 2:0] (
RS690M only
)
I/O
VDDR
VSS
–
Debug port signals. See
section 3.14, “Debug Port Signals,”
for details.
DFT_GPIO[5:0]
I/O
VDD_18
VSS
–
GPIO for DFT purpose.
I2C_CLK
I/O
VDDR3
VSS
50k
Ω
programmable:
PU/PD/none
I
2
C interface clock signal. Can also be used simultaneously as
DDC interface clock for more than one display. It can also be used
as GPIO.
I2C_DATA
I/O
VDDR3
VSS
50k
Ω
programmable:
PU/PD/none
I
2
C interface data signal. It can also be used as GPIO.
DDC_DATA
I/O
VDDR3
VSS
50k
Ω
programmable:
PU/PD/none
Pin for additional DDC data channel for displays. It makes use of
I2C_CLK to create an I
2
C interface. Can also be used as GPIO.
NC
–
–
–
–
No connect. These pins should be left unconnected to anything.
STRP_DATA
I/O
VDDR3
VSS
50k
Ω
programmable:
PU/PD/none
I2C interface data signal for external EEPROM based strap
loading. Can also be used as GPIO, or as output to the voltage
regulator for pulse-width modulation of RS690M’s core voltage.
TESTMODE
I
VDDR3
VSS
–
When high, puts the RS690M in test mode and disables the
RS690M from operating normally.
THERMALDIODE_P,
THERMALDIODE_N
A-O
–
–
–
Diode connections to external SMBus microcontroller for
monitoring IC thermal characteristics.
Table 3-10 TMDS Interface Multiplexed on the PCI Express
®
Graphics Interface (Continued)
Pin Name
Ball
Reference
TMDS Function