Power Management for the Graphics Controller
© 2008 Advanced Micro Devices, Inc.
41978 AMD RS690M Databook 3.06
Proprietary
6-5
6.2.6
Next Item Pointer
The Next Item Pointer
register describes the location of the next item in the capability list of the function. The value given
is an offset in the PCI Configuration Space of that function. This register must be set to 00h if the function does not
implement any other capabilities defined by the PCI Specifications for inclusion in the capabilities list, or if power
management is the last item in the list.
6.2.7
PMC - Power Management Capabilities (Offset = 2)
The Power Management Capabilities
register is a 16-bit Read Only register that provides information on the capabilities
of the function related to power management. The information in this register is generally static and is known at design
time.
Table 6-9 Next Item Pointer (NEXT_ITEM_PTR)
Bits
Default
Value
Read/
Write
Description
7:0
80h
Read Only
This field provides an offset in the PCI Configuration Space of the function pointing to the location
of next item in the capability list of the function. For Power Management of the RS690M, this
pointer is set to 80h and it points to the next capability pointer of the MSI structure.
Table 6-10 Power Management Capabilities – PMC
Bits
Default Value
Read/
Write
Description
15:11
00111b
Read Only
This 5-bit field indicates the power states in which the function may assert PME#. A value of
0b for any bit indicates that the function is not capable of asserting the PME# signal while in
that power state.
bit(11) XXXX1b - PME# can be asserted from D0.
bit(12) XXX1Xb - PME# can be asserted from D1.
bit(13) XX1XXb - PME# can be asserted from D2.
bit(14) X0XXXb - PME# cannot be asserted from D3hot.
bit(15) 0XXXXb - PME# cannot be asserted from D3cold.
10
1b
Read Only
RS690M supports D2.
Cap_Ptr = 50h
8 bits
PCI Configuration Header
Offset 34h
02
5Ch
AGP Capability
01
00h
PM Registers
Offset 5Ch
Offset 50h
Figure 6-1 Linked List for Capabilities
