41978 AMD RS690M Databook 3.06
© 2008 Advanced Micro Devices, Inc.
3-12
Proprietary
TMDS Interface Multiplexed on the PCI Express® Graphics Lanes (Not
Applicable to the RS690MC)
3.9
TMDS Interface Multiplexed on the PCI Express
®
Graphics Lanes (Not Applicable to the
RS690MC)
The RS690M supports a dual-link TMDS interface, enabling DVI/HDMI, which is multiplexed on the PCI-E external
graphics lanes. The TMDS interface is available only if no external graphics card is attached to the PCI-E graphics
interface.
HDMI is enabled only through the single-link mode.
Table 3-10, “TMDS Interface Multiplexed on the PCI Express®
shows the multiplexing relationships between the PCI-E external graphics signals and the TMDS
signals.
LVDS_BLON
I/O
VDDR3
VSS
50k
Ω
programmable:
PU/PD/none
Digital panel backlight brightness control. Active high. It controls
backlight on/off or acts as PWM output to adjust brightness.
If LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_EN = 0, the pin
controls backlight on/off. Otherwise, it is the PWM output to adjust
the brightness.
LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_LEVEL can be used
to control the backlight level (256 steps) by means of pulse width
modulation. The duty cycle of the backlight signal can be set
through the LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_LEVEL
bits. For example, setting these bits to a value of 32 will set the
on-time to 32/256*(1/f) and the off-time to (256-32)/256*(1/f),
where f is the XTALIN frequency and is typically 14.318MHz.
Note that the PWM frequency is set by
LVTMA_BL_MOD_CNTL.LVTMA_BL_MOD_RES and
LVTMA_PWRSEQ_REF_DIV.LVTMA_BL_MOD_REF_DIV. The
PWM frequency
= f/((BL_MOD_1)*(BL_1)).
For more information, refer to the
Register Reference Manual
.
In CPIS mode, LVDS_BLON is VARY_BL as defined in CPIS.
PWM mode should be enabled. LVDS_BLEN should be
connected to ENA_BL, which turns the backlight AC inverter
on/off.
LVDS_DIGON
I/O
VDDR3
VSS
50k
Ω
programmable:
PU/PD/none
Control Panel Digital Power On/Off. Active high.
LVDS_BLEN
I/O
VDDR3
VSS
50k
Ω
programmable:
PU/PD/none
Enables Backlight for CPIS compliant LCD panels. Active high.
Controlled by the hardware power up/down sequencer. For more
details, refer to
Figure 4-2, “LCD Panel Power Up/Down
Table 3-10 TMDS Interface Multiplexed on the PCI Express
®
Graphics Interface
Pin Name
Ball
Reference
TMDS Function
GFX_TX0P
J1
TX2P - 1st Link Red+
GFX_TX0N
H2
TX2M - 1st Link Red-
GFX_TX1P
K2
TX1P - 1st Link Green+
GFX_TX1N
K1
TX1M - 1st Link Green-
GFX_TX2P
K3
TX0P - 1st Link Blue+
GFX_TX2N
L3
TX0M- 1st Link Blue -
GFX_TX3P
L1
TXCP - Clock+
GFX_TX3N
L2
TXCM - Clock-
GFX_TX4P
N2
TX5P- 2nd Link Red+
GFX_TX4N
N1
TX5M - 2nd Link Red-
Table 3-9 LVDS Interface (Continued)
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
Termination
Functional Description