© 2008 Advanced Micro Devices, Inc.
41978 AMD RS690M Databook 3.06
Proprietary
B-3
Features of the TMDS/DVI output include:
•
Supports a 30-bit dual-link DVI interface.
•
1650 Mbps/channel with 165MHz pixel clock rate per link (data rate and clock speed to be qualified).
•
Supports industry standard EVA-861B video modes including 480p, 720p, and 1080i. For a full list of currently
supported modes, contact your AMD CSS representative.
Figure B-3 RS690E LVTM Interface
Notice that the RS690E, like the RS690T, can also provide a TMDS/DVI via its TMDS interface that is multiplexed with
its PCI Express graphics link. As a result, the RS690E can provide two single-link DVI-D outputs using its two on-chip
integrated TMDS transmitters—one through the LVTM interface, and the other through the TMDS interface multiplexed
with the PCI-E graphics interface.
B.3
DVI-I Support
The RS690E has the capability of driving both digital and analog outputs simultaneously to a DVI-I connector. This is
accomplished by routing the RED, GREEN, BLUE, DACHSYNC, DACVSYNC, and AVSSN signals from the
RS690E’s CRT output (see
Figure B-2, “RS690T and RS690E Analog Display Output Signals”
) to the DVI-I connector’s
C1(R), C2(G), C3(B), C4(HS), C5(GND), and Pin 8 (VS) signals (see
Figure B-4, “Pins for Analog Output on the DVI-I
below).
Figure B-4 Pins for Analog Output on the DVI-I Connector
For the single-link DVI output portion of the DVI-I connector, AMD recommends using the RS690E’s LVTM interface to
provide the DVI output and routing these digital signals (see
Figure B-3, “RS690E LVTM Interface”
inputs on the DVI-I connector. The video BIOS must be configured so that the RS690E drives out DVI/TMDS from its
LVTM interface. Display modes supported include desktop resolutions such as 800x600, 1024x768, 1152x864,
1280x1024, and 1600x1200 at 16bpp or 32bpp, with 60Hz or 75Hz screen refresh rate.
TXOUT_U0N/P
TXOUT_U1N/P
TXOUT_U2N/P
TXCLK_LN/P
TXOUT_L0N/P
TXCLK_UN/P
TXOUT_L1N/P
TXOUT_L2N/P
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
LVDS upper data channel 0
LVDS upper data channel 2
LVDS lower clock channel
LVDS lower data channel 0
LVDS upper clock channel
LVDS lower data channel 1
LVDS lower data channel 2
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
LVDS upper data channel 3
TXOUT_U3N/P
LVDS upper data channel 1
TXOUT_U0N/P
TXOUT_U1N/P
TXOUT_U2N/P
TXCLK_LN/P
TXOUT_L0N/P
TXCLK_UN/P
TXOUT_L1N/P
TXOUT_L2N/P
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
TMDS data channel 4
TMDS data channel 0
NC
TMDS data channel 3
TMDS clock channel
TMDS data channel 2
NC
GPIO3
GPIO2
GPIO4
TMDS data channel 1
TXOUT_U3N/P
TMDS data channel 5
TXOUT_L3N/P
LVDS lower data channel 3
TXOUT_L3N/P
NC
LVTM Interface in LVDS Mode
LVTM Interface in TMDS Mode
VGA Signals