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AMD RS690M, Technical Reference Manual

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AMD RS690M Technical Reference Manual Download Page 35

DVI/HDMI (Not Applicable to the RS690MC)

© 2008 Advanced Micro Devices, Inc.

41978 AMD RS690M Databook 3.06

Proprietary

2-11

Table 2-6  Dual-Link Signal Mapping for DVI 

Link 1

Link 2

DVI Functional 

Name

Data Phase

Signal

DVI Functional 

Name

Data Phase

Signal

TX0M/P

Phase 1

EVEN_B0

TX3M/P

Phase 1

ODD_B0

Phase 2 

EVEN_B1

Phase 2 

ODD_B1

Phase 3

EVEN_B2

Phase 3

ODD_B2

Phase 4

EVEN_B3

Phase 4

ODD_B3

Phase 5

EVEN_B4

Phase 5

ODD_B4

Phase 6

EVEN_B5

Phase 6

ODD_B5

Phase 7

EVEN_B6

Phase 7

ODD_B6

Phase 8

EVEN_B7

Phase 8

ODD_B7

Phase 9

EVEN_B8

Phase 9

ODD_B8

Phase 10

EVEN_B9

Phase 10

ODD_B9

TX1M/P

Phase 1

EVEN_G0

TX4M/P

Phase 1

ODD_G0

Phase 2

EVEN_G1

Phase 2

ODD_G1

Phase 3

EVEN_G2

Phase 3

ODD_G2

Phase 4

EVEN_G3

Phase 4

ODD_G3

Phase 5

EVEN_G4

Phase 5

ODD_G4

Phase 6

EVEN_G5

Phase 6

ODD_G5

Phase 7

EVEN_G6

Phase 7

ODD_G6

Phase 8

EVEN_G7

Phase 8

ODD_G7

Phase 9

EVEN_G8

Phase 9

ODD_G8

Phase 10

EVEN_G9

Phase 10

ODD_G9

TX2M/P

Phase 1

EVEN_R0

TX5M/P

Phase 1

ODD_R0

Phase 2

EVEN_R1

Phase 2

ODD_R1

Phase 3

EVEN_R2

Phase 3

ODD_R2

Phase 4

EVEN_R3

Phase 4

ODD_R3

Phase 5

EVEN_R4

Phase 5

ODD_R4

Phase 6

EVEN_R5

Phase 6

ODD_R5

Phase 7

EVEN_R6

Phase 7

ODD_R6

Phase 8

EVEN_R7

Phase 8

ODD_R7

Phase 9

EVEN_R8

Phase 9

ODD_R8

Phase 10

EVEN_R9

Phase 10

ODD_R9

Notes:

- H/VSYNC are transmitted on TX0M/P(Blue) channel during blank.
- For DVI dual-link mode, the first active data pixel is defined as pixel#0 (an even pixel), as opposed to the DVI specifications.

Summary of Contents for RS690M

Page 1: ...AMD RS690M Databook Technical Reference Manual Rev 3 06 P N 41978_rs690m_ds 2008 Advanced Micro Devices Inc ...

Page 2: ...Shader HD SmoothVision HD HyperMemory PowerPlay and PowerShift are trademarks of Advanced Micro Devices Inc HyperTransport is a licensed trademark of the HyperTransport Technology Consortium Macrovision is a registered trademarks of Macrovision Corporation in the United States and or other countries Microsoft Windows DirectX Direct3D DirectDraw and ClearType are registered trademarks and Windows V...

Page 3: ...I HDMI Not applicable to the RS690MC 1 6 1 5 12 Power Management Features 1 6 1 5 13 PC Design Guide Compliance 1 7 1 5 14 Test Capability Features 1 7 1 5 15 Additional Features 1 7 1 5 16 Packaging 1 7 1 6 Software Features 1 7 1 7 Branding Diagrams 1 8 1 7 1 Branding Diagrams for ASIC Revision A11 1 8 1 7 2 Branding Diagrams for ASIC Revision A12 and After 1 9 1 8 Part Number Legend 1 11 1 9 Co...

Page 4: ... II to Southbridge 3 9 3 5 3 4 x 1 Lane Interface for General Purpose External Devices 3 9 3 5 4 Miscellaneous PCI Express Signals 3 9 3 6 Clock Interface 3 10 3 7 CRT and TV Interface 3 10 3 8 LVDS Interface 24 Bits 3 11 3 9 TMDS Interface Multiplexed on the PCI Express Graphics Lanes Not Applicable to the RS690MC 3 12 3 10 Power Management Pins 3 13 3 11 Miscellaneous Pins 3 13 3 12 Power Pins 3...

Page 5: ...apabilities List Data Structure in PCI Configuration Space 6 2 6 2 4 Register Block Definition 6 3 6 2 5 Capability Identifier Cap_ID Offset 0 6 4 6 2 6 Next Item Pointer 6 5 6 2 7 PMC Power Management Capabilities Offset 2 6 5 Chapter 7 Testability 7 1 Test Capability Features 7 1 7 2 Test Interface 7 1 7 3 XOR Tree 7 1 7 3 1 Brief Description of an XOR Tree 7 1 7 3 2 Description of the XOR Tree ...

Page 6: ...abook 3 06 2008 Advanced Micro Devices Inc Table of Contents 4 Proprietary B 3 DVI I Support 2 3 B 4 HDMI 2 4 B 5 HDCP 2 4 B 6 RS690E Display Options 2 4 B 7 The LVTM Interface in TMDS Mode 2 5 Appendix C Revision History ...

Page 7: ...3 RS690T Pin Assignment Left 3 4 Figure 3 4 RS690T Pin Assignment Right 3 5 Figure 3 5 RS690M Interface Block Diagram 3 6 Figure 3 6 RS690T Interface Block Diagram 3 7 Figure 4 1 Power Rail Power Up Sequence for the RS690M 4 4 Figure 4 2 LCD Panel Power Up Down Timing 4 5 Figure 5 1 DC Characteristics of the TMDS Interface 5 4 Figure 5 2 DC Characteristics of the LVDS Interface 5 5 Figure 5 3 RS69...

Page 8: ...41978 AMD RS690M Databook 3 06 2008 Advanced Micro Devices Inc List of Figures 2 Proprietary This page is left blank intentionally ...

Page 9: ...agement Pins 3 13 Table 3 12 Miscellaneous Pins 3 13 Table 3 13 Power Pins 3 14 Table 3 14 Ground Pins 3 15 Table 3 15 RS690M Debug Port Signals 3 17 Table 3 16 RS690T Debug Port Signals 3 17 Table 3 17 Strap Definitions for the RS690M 3 18 Table 3 18 Strap Definition for GPPSB_LINK_CONFIG 3 19 Table 4 1 HTREFCLK Pad 66 66MHz Timing Parameters 4 1 Table 4 2 PCI Express Differential Clock GFX_CLK S...

Page 10: ...ement Control Status Register PMCSR 6 4 Table 6 8 Capability Identifier Cap_ID 6 4 Table 6 9 Next Item Pointer NEXT_ITEM_PTR 6 5 Table 6 10 Power Management Capabilities PMC 6 5 Table 7 1 Pins on the Test Interface 7 1 Table 7 2 Example of an XOR Tree 7 2 Table 7 3 RS690M XOR Tree 7 3 Table 7 4 RS690T XOR Tree 7 4 Table 7 5 Truth Table for the VOH VOL Tree Outputs 7 6 Table 7 6 RS690M VOH VOL Tree...

Page 11: ...M delivers the best Windows Vista experience of any integrated graphics and core logic product for the AMD platform It incorporates an ATI Radeon X700 based graphics core which provides the 3D rendering power needed to generate the Windows Vista desktop even under the most demanding circumstances In addition dedicated hardware acceleration is provided for key new Windows Vista features such as Cle...

Page 12: ... device with respect to their form fit and functionally except for the differences described in Appendix B AMD RS690E All information in this databook that is applicable to the RS690T unless superseded by the information given in Appendix B is also applicable to the RS690E 1 5 RS690M Features 1 5 1 CPU HyperTransport Interface Supports the mobile and desktop Athlon 64 Athlon 64 FX Athlon X2 AMD Se...

Page 13: ...PCI E link Supports programmable lane reversal for the graphics link to ease motherboard layout when the end device does not support lane reversal A four port x4 PCI Express general purpose interface configurable to one of the following modes of support Four x1 links Two x2 links One x2 and two x1 links One x4 link 1 5 5 A Link Express II Interface One x4 A Link Express II interface PCI Express 1 ...

Page 14: ...erformance in true color triple buffered 32bpp acceleration modes New generation rendering engine provides top 3D performance Support for OpenGL format for Indirect Vertices in Vertex Walker Full DirectX 9 0 support Vertex Shader version 2 0 and Pixel Shader version 2 0 Full precision floating point pixel pipeline Support for up to 4 MRTs Multiple Render Targets Support for writing all texture for...

Page 15: ...n controls for main graphics layer Support for DDC1 and DDC2B for plug and play monitors 8 bit alpha blending of graphics and video overlay Hardware cursor up to 64x64 pixels in 2bpp full color AND XOR mix and full color 8 bit alpha blend Hardware icon up to 128x128 pixels in 2bpp with two colors transparent and inverse transparent AND XOR mixing Supports 2x2 icon magnification Virtual desktop sup...

Page 16: ...urrently supported modes contact your AMD CSS representative Maximum resolutions supported by various modes are Single link DVI 1600x1200 60Hz with pixel clock at 162 MHz and standard timings 1920x1200 60Hz with pixel clock at 154MHz and reduced blanking timings Dual link DVI 2560x1600 60Hz with pixel clock at 268 MHz DVI clock at 134 MHz HDMI 1080i with pixel clock at 74MHz HDMI basic audio suppo...

Page 17: ... O s to allow for proper soldering verification at the board level A VOH VOL test mode on all digital I O s to allow for proper verification of output high and output low values at the board level Improved access to the analog modules to allow full evaluation and characterization Improved IDDQ mode support to allow chip evaluation through current leakage measurements These test modes can be access...

Page 18: ...ltaneous view extended desktop support Windows XP and Windows Vista DirectX 9 0 support Switchable overlay support H 264 playback support 1 7 Branding Diagrams 1 7 1 Branding Diagrams for ASIC Revision A11 o GGGGG YYWWXXV 216MQA6AVA11FG TAIWAN RS690M YY Assembly Start Year WW Assembly Start Week XX Assembly Location V Substrate Vendor Code Part Number for ASIC revision A11 Country of Origin Date a...

Page 19: ...ok is specific to the ASIC revision numbers given in the diagrams o GGGGG YYWWXXV 216LQA6AVA11FG TAIWAN RS690MC YY Assembly Start Year WW Assembly Start Week XX Assembly Location V Substrate Vendor Code Part Number for ASIC revision A11 Country of Origin Date and Other Codes Wafer Foundry s Lot Number AMD Code Name Artwork o GGGGG YYWWXXV 216TQA6AVA11FG TAIWAN RS690T YY Assembly Start Year WW Asse...

Page 20: ...Year WW Assembly Start Week XX Assembly Location V Substrate Vendor Code Part Number for ASIC revision A12 Country of Origin Date and Other Codes Wafer Foundry s Lot Number AMD Product Type AMD Logo o indicates pin A1 GGGGGG YYWWXXV COO o 216LQA6AVA12FG CHIPSET YY Assembly Start Year WW Assembly Start Week XX Assembly Location V Substrate Vendor Code Part Number for ASIC revision A12 Country of Or...

Page 21: ... Code Part Number for ASIC revision A12 Country of Origin Date and Other Codes Wafer Foundry s Lot Number AMD Product Type AMD Logo o indicates pin A1 TSMC Fab 215 RQA6 A V A12 F G 215 Desktop 216 Mobile Product Type TQA6 RS690T Marketing Brand Name Substrate Revision N UMC Fab 8F M IBM C 3 S TSMC Fab 4 F TSMC Fab 5 G TSMC Fab6 K TSMC Fab 12 L TSMC Fab14 W TSMC WSMC Q TSMC WSMC 8B T TSMC Wafer Tec...

Page 22: ...ever there is a risk of ambiguity Other numbers are in decimal Pins of identical functions but different trailing integers e g CPU_D0 CPU_D1 CPU_D7 are referred to collectively by specifying their integers in square brackets and with colons i e CPU_D 7 0 A similar short hand notation is used to indicate bit occupation in a register For example NB_COMMAND 15 10 refers to the bit positions 10 throug...

Page 23: ...t In Self Test BLT Blit bpp bits per pixel CEC Consumer Electronic Control CPIS Common Panel Interface Specification CRT Cathode Ray Tube CSP Chip Scale Package DAC Digital to Analog Converter DBI Dynamic Bus Inversion DDC Display Data Channel A VESA standard for communicating between a computer system and attached display devices DDR Double Data Rate DFP Digital Flat Panel Monitor connection stan...

Page 24: ...areas PCI Peripheral Component Interface PCI E PCI Express PCMCIA Personal Computer Memory Card International Association It is also the name of a standard for PC peripherals promoted by the Association PLL Phase Locked Loop POST Power On Self Test PD Pull down Resistor PU Pull up Resistor ROP Raster Operation SDRAM Synchronous Dynamic RAM TMDS Transition Minimized Differential Signaling UMA Unifi...

Page 25: ...faces Figure 2 1 RS690M Internal Block Diagram Hyper Transport Unit CPU Interface Register Interface iDCT Setup Engine 2D Engine 3D Engine Overlay Root MUX Display 1 2 TV Out LVDS CRT Memory Controller AMD CPU BIF Complex Optional 16 bit DDR2 Memory Channel RS690T Only on PCI E Gfx lanes TMDS enabling DVI HDMI Multiplexed SB External Graphics A Link E II Gfx Interface PCI E Interface 1 x 16 Lanes ...

Page 26: ... layer and the protocol transaction layer The PHY is the physical interface between the RS690M and the CPU The data link layer includes the initialization and configuration sequences periodic redundancy checks connect disconnect sequences and information packet flow controls The protocol layer is responsible for maintaining strict ordering rules defined by the HT protocol The RS690M HyperTransport...

Page 27: ...ases the memory bandwidth and reduces data latency to the integrated graphics core The additional bandwidth provided to the internal graphics core will also aid the RS690T in reaching and exceeding Microsoft s Windows VistaTM Premium logo requirements 2 2 1 DDR2 Memory Interface Figure 2 4 RS690T Side port Memory Interface on page 2 4 illustrates the side port memory interface of the RS690T The RS...

Page 28: ...ing Table 2 1 Supported DDR2 Components DDR2 SDRAM Mbytes Config Mbits CS Mode Bank Bits Row Bits Col Bits 16Mbits x 16 256 4 2 13 9 32 32Mbits x 8 256 5 2 13 10 64 32Mbits x 16 512 10 2 13 10 64 64Mbits x 8 512 6 2 14 10 128 64Mbits x 16 1024 11 3 13 10 128 Address A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16Mbits x16 devices Row P10 P14 P13 P12 P11 P22 P21 P20 P19 P18 P17 P16 P15 Column PC P...

Page 29: ... P19 P18 P17 P16 P15 Column PC P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 64Mbits x8 devices Row P24 P23 P14 P13 P12 P11 P22 P21 P20 P19 P18 P17 P16 P15 Column PC P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 64Mbits x16 devices Row P23 P14 P13 P12 P11 P22 P21 P20 P19 P18 P17 P16 P15 Column PC P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 Note PC precharge flag Address A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ...

Page 30: ...The signal mappings for single and dual channel transmission are shown in Table 2 3 and Table 2 4 respectively Figure 2 5 Single Dual Channel 24 bit LVDS Data Transmission Ordering LP1C1 LP1C2 LP1C3 T Cycle LP1C4 LP1C5 LP1C6 LP1C7 TXOUT_L0 LP2C1 LP2C2 LP2C3 LP2C4 LP2C5 LP2C6 LP2C7 TXOUT_L1 LP3C1 LP3C2 LP3C3 LP3C4 LP3C5 LP3C6 LP3C7 TXOUT_L2 TXCLK_L LP4C1 LP4C2 LP4C3 LP4C4 LP4C5 LP4C6 LP4C7 TXOUT_L3...

Page 31: ...ixel per Clock Single Channel Signal Mapping TX Signal 24 bit LP1C1 R0 LP1C2 R1 LP1C3 R2 LP1C4 R3 LP1C5 R4 LP1C6 R5 LP1C7 G0 LP2C1 G1 LP2C2 G2 LP2C3 G3 LP2C4 G4 LP2C5 G5 LP2C6 B0 LP2C7 B1 LP3C1 B2 LP3C2 B3 LP3C3 B4 LP3C4 B5 LP3C5 HSYNC LP3C6 VSYNC LP3C7 ENABLE LP4C1 R6 LP4C2 R7 LP4C3 G6 LP4C4 G7 LP4C5 B6 LP4C6 B7 LP4C7 Reserved ...

Page 32: ...p to 5 and the modulation frequency in the range of 20 50kHz are programmable through the LVDS registers TX Signal 24 bit TX Signal 24 bit LP1C1 Ro0 UP1C1 Re0 LP1C2 Ro1 UP1C2 Re1 LP1C3 Ro2 UP1C3 Re2 LP1C4 Ro3 UP1C4 Re3 LP1C5 Ro4 UP1C5 Re4 LP1C6 Ro5 UP1C6 Re5 LP1C7 Go0 UP1C7 Ge0 LP2C1 Go1 UP2C1 Ge1 LP2C2 Go2 UP2C2 Ge2 LP2C3 Go3 UP2C3 Ge3 LP2C4 Go4 UP2C4 Ge4 LP2C5 Go5 UP2C5 Ge5 LP2C6 Bo0 UP2C6 Be0 L...

Page 33: ...ink with the first link transmitting data for even pixels and the second link for odd pixels See Table 2 6 Dual Link Signal Mapping for DVI on page 2 11 for details The signal mapping for the transmission is shown in Table 2 5 Single Link Signal Mapping for DVI HDMI on page 2 10 and Table 2 6 Dual Link Signal Mapping for DVI on page 2 11 TX0P TX0M TX1P TX1M TX2P TX2M TXCP TXCM TG9 TG8 TG7 TG6 TG5 ...

Page 34: ...0M P Phase 1 B0 Phase 2 B1 Phase 3 B2 Phase 4 B3 Phase 5 B4 Phase 6 B5 Phase 7 B6 Phase 8 B7 Phase 9 B8 Phase 10 B9 TX1M P Phase 1 G0 Phase 2 G1 Phase 3 G2 Phase 4 G3 Phase 5 G4 Phase 6 G5 Phase 7 G6 Phase 8 G7 Phase 9 G8 Phase 10 G9 TX2M P Phase 1 R0 Phase 2 R1 Phase 3 R2 Phase 4 R3 Phase 5 R4 Phase 6 R5 Phase 7 R6 Phase 8 R7 Phase 9 R8 Phase 10 R9 Note H VSYNC are transmitted on TX0M P Blue chan...

Page 35: ...hase 1 ODD_G0 Phase 2 EVEN_G1 Phase 2 ODD_G1 Phase 3 EVEN_G2 Phase 3 ODD_G2 Phase 4 EVEN_G3 Phase 4 ODD_G3 Phase 5 EVEN_G4 Phase 5 ODD_G4 Phase 6 EVEN_G5 Phase 6 ODD_G5 Phase 7 EVEN_G6 Phase 7 ODD_G6 Phase 8 EVEN_G7 Phase 8 ODD_G7 Phase 9 EVEN_G8 Phase 9 ODD_G8 Phase 10 EVEN_G9 Phase 10 ODD_G9 TX2M P Phase 1 EVEN_R0 TX5M P Phase 1 ODD_R0 Phase 2 EVEN_R1 Phase 2 ODD_R1 Phase 3 EVEN_R2 Phase 3 ODD_R...

Page 36: ...al active on line selected by software 0x04 ACP Packet Yes Audio content protection information 0x05 ISRC1 Packet Yes Controlled by video driver Inserted in horizontal active on line selected by software For transmitting UPC or ISRC codes 0x06 ISRC2 Packet Yes Software controlled Inserted in horizontal active on line selected by software Implement if ISRC1 is used 0x07 Reserved N A N A N A InfoFra...

Page 37: ...from the end of the overshoot to the point where the amplitude of the video ringing is down to 5 of the final steady state value 8 This parameter is sampled not 100 tested 9 Monotonicity is guaranteed 10 Levels are 7 8 higher with setup pedestal enabled 2 6 External Clock Chip On the RS690M platform an external clock chip provides the reference clock to the CPU for generating the CPU internal cloc...

Page 38: ...41978 AMD RS690M Databook 3 06 2008 Advanced Micro Devices Inc 2 14 Proprietary External Clock Chip This page is left blank intentionally ...

Page 39: ...ress Interfaces on page 3 9 1 x 16 Lane Interface for External Graphics Not Applicable to the RS690MC on page 3 9 A Link Express II to Southbridge on page 3 9 4 x 1 Lane Interface for General Purpose External Devices on page 3 9 Miscellaneous PCI Express Signals on page 3 9 Clock Interface on page 3 10 CRT and TV Interface on page 3 10 LVDS Interface 24 Bits on page 3 11 TMDS Interface Multiplexed...

Page 40: ..._TX1N GFX_TX1P GFX_TX2P L GFX_TX3P GFX_TX3N GFX_TX2N GFX_RX4P GFX_RX4N VSSA GFX_RX3N GFX_RX3P VDDA_12 VDD_CORE VSS VDD_CORE M VDDA_12_PKG VSSA VSSA GFX_RX6P GFX_RX6N VSSA GFX_RX5N GFX_RX5P VDDA_12 VSS VDD_CORE VSS N GFX_TX4N GFX_TX4P VSSA VDD_CORE VSS VDD_CORE P GFX_TX5N GFX_TX5P GFX_TX6P GFX_RX8P GFX_RX8N VSSA GFX_RX7N GFX_RX7P VSSA VSS VDD_CORE VSS R GFX_TX7P GFX_TX7N GFX_TX6N GFX_RX9P GFX_RX9N ...

Page 41: ...3P VSS HT_TXCAD6N VSS M VSS VDD_CORE HT_TXCTLP HT_TXCAD7P HT_TXCAD7N N VDD_CORE VSS VDD_CORE HT_TXCAD14P HT_TXCAD14N VSS HT_TXCAD15P HT_TXCAD15N HT_TXCTLN HT_RXCTLP HT_RXCTLN P VSS VDD_CORE VSS HT_RXCAD15N HT_RXCAD15P VSS HT_RXCAD14P HT_RXCAD14N VSS VSS HT_RXCAD7N R VSS HT_RXCAD7P VSS T VDD_CORE VDD_CORE HT_RXCAD12P HT_RXCAD12N VSS HT_RXCAD13N HT_RXCAD13P HT_RXCAD5N HT_RXCAD6N HT_RXCAD6P U VSSA VS...

Page 42: ...1P GFX_TX2P L GFX_TX3P GFX_TX3N GFX_TX2N GFX_RX4P GFX_RX4N VSSA GFX_RX3N GFX_RX3P VDDA_12 VDD_CORE VSS VDD_CORE M VDDA_12_PKG VSSA VSSA GFX_RX6P GFX_RX6N VSSA GFX_RX5N GFX_RX5P VDDA_12 VSS VDD_CORE VSS N GFX_TX4N GFX_TX4P VSSA VDD_CORE VSS VDD_CORE P GFX_TX5N GFX_TX5P GFX_TX6P GPP_RX2P GPP_RX2N VSSA GFX_RX7N GFX_RX7P VSSA VSS VDD_CORE VSS R GFX_TX7P GFX_TX7N GFX_TX6N GPP_RX3P GPP_RX3N VSSA GPP_RX0...

Page 43: ...SS M VSS VDD_CORE HT_TXCTLP HT_TXCAD7P HT_TXCAD7N N VDD_CORE VSS VDD_CORE HT_TXCAD14P HT_TXCAD14N VSS HT_TXCAD15P HT_TXCAD15N HT_TXCTLN HT_RXCTLP HT_RXCTLN P VSS VDD_CORE VSS HT_RXCAD15N HT_RXCAD15P VSS HT_RXCAD14P HT_RXCAD14N VSS VSS HT_RXCAD7N R VSS HT_RXCAD7P VSS T VDD_CORE VDD_CORE HT_RXCAD12P HT_RXCAD12N VSS HT_RXCAD13N HT_RXCAD13P HT_RXCAD5N HT_RXCAD6N HT_RXCAD6P U VSS MEM_CKN HT_RXCAD5P HT_...

Page 44: ...XCLK_UP TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P GFX_TX 15 0 P GFX_TX 15 0 N GFX_RX 15 0 P GFX_RX 15 0 N GFX_CLKP GFX_CLKN VSSA AVSSN LPVSS LVSSR AVSSQ TESTMODE THERMALDIDOE_N TVCLKIN OSCIN SYSRESET POWERGOOD VDD_18 VDDR3 PLLVDD18 VDD_CORE VDDA_12 PLLVSS C Y COMP RSET RED GREEN DACSCL DACSDA DACHSYNC DACVSYNC BLUE THERMALDIODE_P HyperTransport Interface LVDS Interface A Link Express II Interface Po...

Page 45: ...IN SYSRESET POWERGOOD VDD_18 VDDR3 PLLVDD18 VDD_CORE VDDA_12 MEM_CS C Y COMP RSET RED GREEN DACSCL DACSDA DACHSYNC DACVSYNC BLUE THERMALDIODE_P HyperTransport Interface LVDS Interface A LinkExpress Interface Power Management Interface Misc Signals PCI E External Graphics or TMDS Interface CRT and TV out Interface Clock Interface Power Side port Memory VDD_HT MEM_CAS LVDS_DIGON LVDS_BLON PCI E Inte...

Page 46: ...ion Resistor to HTTX_CALN HT_TXCALN Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALP Table 3 2 DDR2 Side port Memory Interface RS690T Only Pin Name Type Power Domain Ground Domain Integrated Termination Functional Description MEM_A 13 0 O VDD_MEM VSS None Memory Address Bus Provides the multiplexed row and column addresses to the memories MEM_BA 2 0 O VDD_MEM VSS None Memory Bank Addr...

Page 47: ...ain Integrated Termination Functional Description SB_TX 3 0 P SB_TX 3 0 N O VDD_PCIE VSS_PCIE 50Ω between complements Transmit Data Differential Pairs Connect to the corresponding Receive Data Differential pairs on the Southbridge SB_RX 3 0 P SB_RX 3 0 N I VDD_PCIE VSS_PCIE 50Ω between complements Receive Data Differential Pairs Connect to the corresponding Transmit Data Differential pairs on the ...

Page 48: ...idge and general purpose PCI Express PCI E devices Connect to an external clock generator on the motherboard OSCIN I VDDR3 VSS Disabled 14 3181818MHz Reference clock input from the External Clock chip 3 3 volt signaling Table 3 8 CRT and TV Interface Pin Name Type Power Domain Ground Domain Integrated Termination Functional Description RED A O AVDD AVSSN Red for CRT monitor output Cr or Pr for com...

Page 49: ...VSSR None LVDS upper clock channel Only used in dual channel LVDS mode TXOUT_L0N O LVDDR33 LVDDR18D LVSSR None LVDS lower data channel 0 This channel is used as the transmitting channel in single channel LVDS mode TXOUT_L0P O LVDDR33 LVDDR18D LVSSR None LVDS lower data channel 0 This channel is used as the transmitting channel in single channel LVDS mode TXOUT_L1N O LVDDR33 LVDDR18D LVSSR None LVD...

Page 50: ..._LEVEL bits For example setting these bits to a value of 32 will set the on time to 32 256 1 f and the off time to 256 32 256 1 f where f is the XTALIN frequency and is typically 14 318MHz Note that the PWM frequency is set by LVTMA_BL_MOD_CNTL LVTMA_BL_MOD_RES and LVTMA_PWRSEQ_REF_DIV LVTMA_BL_MOD_REF_DIV The PWM frequency f BL_MOD_REF_DIV 1 BL_MOD_RES 1 For more information refer to the Register...

Page 51: ...signal to the Southbridge indicates that there is a DMA request from a PCI Express Bus device The signal is not used on the RS690M platforms and should be left unconnected DEBUG 15 13 10 9 6 2 0 RS690M only I O VDDR VSS Debug port signals See section 3 14 Debug Port Signals on page 3 16 for details DFT_GPIO 5 0 I O VDD_18 VSS GPIO for DFT purpose I2C_CLK I O VDDR3 VSS 50kΩ programmable PU PD none ...

Page 52: ... the purpose Table 3 13 Power Pins Pin Name Voltage Pin Count Ball Reference Comments AVDD 2 5V or 3 3V 2 B22 C22 Dedicated power for the DAC Effort should be made at the board level to provide as clean a power as possible to this pin to avoid noise injection which can affect display quality Adequate decoupling should be provided between this pin and AVSS AVDDQ 1 8V 1 A21 DAC Bandgap Reference Vol...

Page 53: ...n PLLVDD18 1 8V 1 A10 1 8V power for system PLLs PLLVDD12 1 2V 1 A11 1 2V power for system PLLs HTPVDD 1 8V 1 B24 Power for HyperTransport interface PLL Total Power Pin Count RS690M 88 RS690T 89 Table 3 14 Ground Pins Pin Name Pin Count Ball Reference Comments AVSSN 2 G17 H17 Dedicated analog ground for the DAC AVSSQ 1 A22 Dedicated ground for the Band Gap Reference Effort should be made at the bo...

Page 54: ...2 L12 L14 L20 L23 L24 M11 M13 M15 M17 M20 M23 M25 N12 N14 P11 P13 P15 P20 R12 R14 R17 R20 R23 R24 T23 T25 U20 W23 W24 Y22 Y23 Y25 RS690T A23 A25 AA14 AB19 AC10 AC12 AC18 AC22 AC23 AD25 AE14 AE18 B7 C4 D23 D25 D4 E9 F11 F17 G11 G23 G24 H12 H23 H25 J12 J22 L12 L14 L20 L23 L24 M11 M13 M15 M17 M20 M23 M25 N12 N14 P11 P13 P15 P20 R12 R14 R17 R20 R23 R24 T23 T25 U20 V11 V14 W17 W23 W24 Y12 Y22 Y23 Y25 C...

Page 55: ... Debug0 to Debug15 Table 3 16 RS690T Debug Port Signals Pin Name Ball Ref Debug Port Name MEM_A0 W12 Debug0 MEM_A1 AD10 Debug1 MEM_A2 AB12 Debug2 MEM_A3 AB11 Debug3 MEM_A4 W14 Debug4 MEM_A5 AB15 Debug5 MEM_A6 AB14 Debug6 MEM_A7 AE9 Debug7 MEM_A8 AA12 Debug8 MEM_A9 AC9 Debug9 MEM_A10 AE10 Debug10 MEM_A11 Y14 Debug11 MEM_A12 AD9 Debug12 MEM_A13 AA11 Debug13 MEM_BA0 AC11 Debug14 MEM_BA1 AE11 Debug15 ...

Page 56: ...the strap pins are undriven allowing either an internal pull up to pull a pin to 1 or an external pull down to pull a pin to 0 The values on the strap pins are then latched into the device and used as operational parameters However for debug purposes those latched values may be overridden through an external debug strap port or by a bit stream downloaded from a serial EEPROM Table 3 17 Strap Defin...

Page 57: ... 4 2 1 1 0 D 0 1 0 4 1 1 1 1 E Others Use register field STRAP_BIF_LINK_CONFIG_GPPSB of register StrapsOutputMux_7 NBMISCIND 0x67 bit 7 4 to define link configuration Note The three strap pins are internally pulled up so that if left unconnected on the motherboard the RS690M will use register field STRAP_BIF_LINK_CONFIG_GPPSB of register StrapsOutputMux_7 NBMISCIND 0x67 bit 7 4 to define the link ...

Page 58: ...41978 AMD RS690M Databook 3 06 2008 Advanced Micro Devices Inc 3 20 Proprietary Strapping Options This page intentionally left blank ...

Page 59: ... setup and hold time to capture the memory data This DLL delay is programmable through the following registers MCA_DLL_SLAVE_RD_0 MCA_DLL_ADJ_DQSR_0 NBMCIND 0xE0 7 0 MCA_DLL_SLAVE_RD_1 MCA_DLL_ADJ_DQSR_1 NBMCIND 0xE1 7 0 Table 4 1 HTREFCLK Pad 66 66MHz Timing Parameters Symbol Parameter Min Typ Max Unit Comment TIP REFCLK Period 15 ns Time intervals measured at 50 VDDCK threshold point FIP REFCLK ...

Page 60: ...od is 5ns then DQS0 is delayed internally by 2 5ns with respect to DQ 7 0 Depending on the board layout of DQS and DQ signals it may be necessary to have different delays for each DQS signal Layouts of the DQS and DQ signals should follow the rules given in the RS690 RS485 Series IGP Motherboard Design Guide 4 5 LVDS Timing 4 6 OSCIN Timing Table 4 3 Timing Requirements for the LVDS Interface Para...

Page 61: ...rement 300 ps FRQD Frequency Tolerance 30 ppm 3 Notes 1 Time intervals measured at 50 threshold point 2 FIP is the reciprocal of TIP 3 FRQD is the tolerance of the frequency input for proper generation of the expected PLL frequencies Table 4 4 Timing Requirements for the OSCIN Pad Continued Symbol Parameter Min Typical Max Unit Note ...

Page 62: ...0 No restrictions T13 1 8V display and PLL rails ramp high relative to 1 2V PLL rails 0 No restrictions T14 1 2V PLL rails ramp high relative to VDD_CORE 1 2V 0 No restrictions Notes 1 Power rails in the same group may require separate power sources Please refer to the RS690 RS485 series IGP Motherboard Design Guide for details 2 There are no specific requirements for the following 1 2V rails VDD_...

Page 63: ...a clock to LVDS_BLON active M N2 T3 Delay from LVDS_BLON inactive to LVDS inactive M N3 T4 Delay from LVDS inactive to LVDS_DIGON inactive M N4 Note Values for M N1 N2 N3 and N4 are programmable through the following registers M LVTMA_PWRSEQ_REF_DIV LVTMA_PWRSEQ_REF_DIV 1 255 N1 LVTMA_PWRSEQ_DELAY1 LVTMA_PWRUP_DELAY1 0 15 N2 LVTMA_PWRSEQ_DELAY1 LVTMA_PWRUP_DELAY2 0 15 N3 LVTMA_PWRSEQ_DELAY1 LVTMA_...

Page 64: ...41978 AMD RS690M Databook 3 06 2008 Advanced Micro Devices Inc 4 6 Proprietary LCD Panel Power Up Down Timing This page is left blank intentionally ...

Page 65: ... V I O power for HyperTransportTM interface VDDR3 3 135 3 3 3 465 V 3 3 Volt I O power VDDA_12 1 14 1 2 1 26 V PCI Express Interface main I O power AVDDDI 1 71 1 8 1 89 V Digital power for DAC AVDDQ 1 71 1 8 1 89 V Band gap reference voltage for DAC AVDD 3 135 3 3 3 465 V I O power for DAC LPVDD 1 71 1 8 1 89 V Power for LVDS PLL macro LVDDR18D 1 71 1 8 1 89 V 1 8V power LVDDR33 3 135 3 3 3 465 V ...

Page 66: ...C_CLK have different values for IOL and IOH DACSCL IOL 14mA IOH 5 8mA I2C_CLK IOL 9 5mA IOH 3 2mA Other numbers in this tables are applicable to the two signals Table 5 3 DC Characteristics for 1 8V TTL Signals Pins Symbol Description Minimum Maximum Unit DFT_GPIO 5 0 VILdc DC voltage at PAD pin that will produce a stable low at the Y pin of macro 0 69 V VIHdc DC voltage at PAD pin that will produ...

Page 67: ...ice VOI Output Low Voltage 0 186V 0 305V I_out 16 5mA VOH Output High Voltage 1 90V 2 50V I_out 16 5mA VREF DC Input Reference Voltage 1 125V 1 375V ILI Input Leakage Current 10µA 15µA ILO Tri state Leakage Current 10µA 15µA CIN Input Capacitance 3pF 5pF Table 5 7 DC Characteristics for the TMDS Interface Multiplexed on the PCI Express Gfx Lanes Symbol Parameter Minimum Typical Maximum Unit Note V...

Page 68: ...0 454 V 1 VSW Single ended Output Swing 257 454 mV 1 VOS Differential Output Overshoot Ringing 160 mV 1 VUS Differential Output Undershoot Ringing 160 mV 1 IDDLP Average Supply Current at 10 0 mA 2 IDDLV Average Supply Current at 100 0 mA 2 IPDLP Power Down Current at 10 0 µA 3 IPDLV Power Down Current at 10 0 µA 3 Notes 1 Differential termination is 100 ohms 2 Measured under typical conditions at...

Page 69: ...rameters and other thermal design descriptions including package level thermal data and analysis please consult the Thermal Design and Analysis Guidelines for the RS690 Product Family 5 2 1 RS690M Thermal Limits Table 5 9 RS690M Thermal Limits Parameter Minimum Nominal Maximum Unit Note Operating Case Temperature 0 95 C 1 Absolute Rated Junction Temperature 125 C 2 Storage Temperature 40 60 C VSW ...

Page 70: ... on the methodology given in the document Thermal Design and Analysis Guidelines for the RS690 Product Family Chapter 10 This is the temperature at which the functionality of the chip is qualified 2 The maximum absolute rated junction temperature is the junction temperature at which the device can operate without causing damage to the ASIC This temperature can be measured via the integrated therma...

Page 71: ...ure 5 4 shows the detailed ball arrangement for the RS690M Figure 5 3 RS690M 690T Package Outline Table 5 10 RS690M 690T 465 Pin FCBGA Package Physical Dimensions Ref Minimum mm Typical mm Maximum mm c 0 96 1 06 1 16 A 2 18 2 33 2 48 A1 0 30 0 40 0 50 A2 0 84 0 87 0 90 φb 0 40 0 50 0 60 D1 20 80 21 00 21 20 D2 7 33 E1 20 80 21 00 21 20 E2 6 93 F1 19 20 F2 19 20 e1 0 80 ddd 0 15 Note Only minimum p...

Page 72: ...s adequate to secure the thermal management device and achieve the lowest thermal contact resistance with a temperature drop across the thermal interface material of no more than 3 C Also the surface flatness of the metal spreader should be 0 001 inch 1 inch Pre test the assembly fixture with a strain gauge to make sure that the flexing of the final assembled board and the pressure applying around...

Page 73: ...Figure 5 5 Stencil Opening Recommendations 5 3 3 2 Reflow Profile A reference reflow profile is given below Please note the following when using RoHS lead free solder SAC105 305 405 Tin Silver Cu The final reflow temperature profile will depend on the type of solder paste and chemistry of flux used in the SMT process Modifications to the reference reflow profile may be required in order to accommo...

Page 74: ... if this condition is violated Maximum 3 reflows are allowed on the same part Figure 5 6 RoHS Lead Free Solder SAC305 405 Tin Silver Copper Reflow Profile Table 5 11 Recommended Board Solder Reflow Profile RoHS Lead Free Solder Profiling Stage Temperature Process Range Overall Preheat Room temp to 220 C 2 mins to 4 mins Soaking Time 130 C to 170 C Typical 60 80 seconds Liquidus 220 C Typical 60 80...

Page 75: ...tes S0 C0 Working State Working State The processor is executing instructions S0 C1 Halt CPU Halt state No instructions are executed This state has the lowest latency on resume and contributes minimum power savings S0 C2 Stop Grant Caches Snoopable Stop Grant or Cache Snoopable CPU state This state offers more power savings but has a higher latency on resume than the C1 state S0 C3 Stop Grant Cach...

Page 76: ...ing Power Status Reporting Setting Power State System Wakeup All four of these capabilities are required for each power management function with the exception of wakeup event generation This section describes the format of the registers in the PCI Configuration Space that are used by these power management operations The Status and Capabilities Pointer CAP_PTR fields have been highlighted to indic...

Page 77: ...ay be accessed as bytes 16 bit words or 32 bit DWORDs All of the write operations to the reserved registers must be treated as no ops This implies that the access must be completed normally on the bus and the data should be discarded Read accesses to the reserved or the unimplemented registers must be completed normally and a data value of 0000h should be returned Table 6 4 PCI Status Register Bit...

Page 78: ...olute offset in the functions PCI Configuration Space to the next item in the list and must be DWORD aligned If there are no more entries in the list the NEXT_ITEM_PTR must be set to 0 to indicate an end of the linked list Each capability can then have registers following the NEXT_ITEM_PTR The definition of these registers including layout size and bit definitions is specific to each capability Th...

Page 79: ...TEM_PTR Bits Default Value Read Write Description 7 0 80h Read Only This field provides an offset in the PCI Configuration Space of the function pointing to the location of next item in the capability list of the function For Power Management of the RS690M this pointer is set to 80h and it points to the next capability pointer of the MSI structure Table 6 10 Power Management Capabilities PMC Bits ...

Page 80: ... beyond the standard PCI configuration header before the generic class device driver is able to use it The RS690M requires device specific initialization after Reset this field must therefore return a value 1 to the system 4 0b Read Only Reserved 3 0b Read Only Reserved 2 0 001b Read Only A value of 001b indicates that this function complies with Revision 1 0 of the PCI Power Management Interface ...

Page 81: ...zation of these modules A JTAG test mode which is not entirely compliant to the IEEE 1149 1 standard to allow board level testing of neighboring devices An XOR TREE test mode on all the digital I Os to allow for proper soldering verification at the board level A VOH VOL test mode on all digital I Os to allow for proper verification of output high and output low voltages at the board level These te...

Page 82: ... JTAG First the 8 bit instruction register of the JTAG is loaded with the XOR instruction 00001000 This instruction assigns the input direction to all the pins except pin TDO which is assigned the output direction to serve as the output of the XOR tree After loading the JTAG is taken to the Run Test state for completion of the XOR tree initialization Note 10MHz clock frequency is recommended for t...

Page 83: ...P V25 V24 25 HT_RXCAD3N P AA24 AA25 26 HT_RXCAD2N P AA23 AB23 27 HT_RXCAD1N P AB25 AB24 28 HT_RXCAD0N P AC25 AC24 29 HT_RXCTLN P P25 P24 30 HT_RXCLK1N P W22 W21 31 HT_RXCLK0N P W25 Y24 32 GPP_RX3N P AA9 AB9 33 GPP_RX2N P AA7 Y7 34 GPP_RX1N P AE20 AD20 35 GPP_RX0N P AE16 AD16 36 SB_RX3N P AB11 AA11 37 SB_RX2N P W12 W11 38 SB_RX1N P AA12 AB12 39 SB_RX0N P W15 W14 40 GFX_RX15N P AB6 AB7 41 GFX_RX14N ...

Page 84: ...A23 AB23 27 HT_RXCAD1N P AB25 AB24 28 HT_RXCAD0N P AC25 AC24 29 HT_RXCTLN P P25 P24 30 HT_RXCLK1N P W22 W21 31 HT_RXCLK0N P W25 Y24 32 GPP_RX3N P R5 R4 33 GPP_RX2N P P5 P4 34 GPP_RX1N P U5 U4 35 GPP_RX0N P R8 R7 36 SB_RX3N P W5 W4 37 SB_RX2N P Y5 Y4 38 SB_RX1N P W9 V9 39 SB_RX0N P AB6 AB7 40 GFX_RX7N P P7 P8 41 GFX_RX6N P M5 M4 42 GFX_RX5N P M7 M8 43 GFX_RX4N P L5 L4 44 GFX_RX3N P L7 L8 45 GFX_RX2...

Page 85: ...e TEST_ODD and TEST_EVEN inputs Sample of a generic VOH VOL tree is shown in the Figure 7 2 below 71 MEM_A10 AE10 72 MEM_A9 AC9 73 MEM_A8 AA12 74 MEM_A7 AE9 75 MEM_A6 AB14 76 MEM_A5 AB15 77 MEM_A4 W14 78 MEM_A3 AB11 79 MEM_A2 AB12 80 MEM_A1 AD10 81 MEM_A0 W12 82 MEM_BA2 AD11 83 MEM_BA1 AE11 84 MEM_BA0 AC11 85 MEM_CAS Y15 86 MEM_RAS AA15 87 MEM_WE AC14 88 MEM_ODT Y9 89 MEM_CS V12 90 MEM_CKE AD12 91...

Page 86: ...y a clock at any speed same or faster than test pattern data rate to the OSCIN pin as the I O test clock source 2 Set POWERGOOD to 0 3 Set TESTMODE to 1 4 Set DACSDA to 0 5 Load JTAG instruction register with the instruction 0110 0011 6 Load JTAG instruction register with the instruction 0010 0111 7 Set POWERGOOD to 1 1 6 5 4 3 2 VOH VOL mode TEST_ODD TEST_EVEN Table 7 5 Truth Table for the VOH VO...

Page 87: ...n Name Ball Ref Control 1 HT_TXCAD15P N P21 P22 EVEN 2 HT_TXCAD14P N P18 P19 ODD 3 HT_TXCAD13P N M22 M21 EVEN 4 HT_TXCAD12P N M18 M19 ODD 5 HT_TXCAD11P N L18 L19 EVEN 6 HT_TXCAD10P N G22 G21 ODD 7 HT_TXCAD9P N J20 J21 EVEN 8 HT_TXCAD8P N F21 F22 ODD 9 HT_TXCTLP N N23 P23 EVEN 10 HT_TXCAD7P N N24 N25 ODD 11 HT_TXCAD6P N L25 M24 EVEN 12 HT_TXCAD5P N K25 K24 ODD 13 HT_TXCAD4P N J23 K23 EVEN 14 HT_TXC...

Page 88: ...ODD 7 HT_TXCAD9P N J20 J21 EVEN 8 HT_TXCAD8P N F21 F22 ODD 9 HT_TXCTLP N N23 P23 EVEN 10 HT_TXCAD7P N N24 N25 ODD 11 HT_TXCAD6P N L25 M24 EVEN 12 HT_TXCAD5P N K25 K24 ODD 13 HT_TXCAD4P N J23 K23 EVEN 14 HT_TXCAD3P N G25 H24 ODD 15 HT_TXCAD2P N F25 F24 EVEN 16 HT_TXCAD1P N E23 F23 ODD 17 HT_TXCAD0P N E24 E25 EVEN 18 DACSCL B6 ODD 19 DACVSYNC C6 EVEN 20 DACHSYNC A5 ODD 21 LVDS_BLON G12 EVEN 22 LVDS_...

Page 89: ...Q8 AD16 ODD 59 MEM_DQ7 AE16 EVEN 60 MEM_DQ6 AE15 ODD 61 MEM_DQ5 AD15 EVEN 62 MEM_DQ2 AC13 ODD 63 MEM_DQ4 AC15 EVEN 64 MEM_DQ1 AE13 ODD 65 MEM_DQ3 AD14 EVEN 66 MEM_DQ0 AD13 ODD 67 MEM_DM1 AD19 EVEN 68 MEM_DM0 AC16 ODD 69 MEM_A13 AA11 EVEN 70 MEM_A12 AD9 ODD 71 MEM_A11 Y14 EVEN 72 MEM_A10 AE10 ODD 73 MEM_A9 AC9 EVEN 74 MEM_A8 AA12 ODD No Pin Name Ball Ref Control 75 MEM_A7 AE9 EVEN 76 MEM_A6 AB14 OD...

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Page 91: ...s pin listings for the RS690M sorted in different ways To go to the listing of interest use the linked cross references below RS690M Pin List Sorted by Ball Reference on page A 2 RS690M Pin List Sorted by Pin Name on page A 6 RS690T Pin List Sorted by Ball Reference on page A 10 RS690T Pin List Sorted by Pin Name on page A 14 ...

Page 92: ...10N AB23 HT_RXCAD2P AB24 HT_RXCAD1P AB25 HT_RXCAD1N AB3 VDDA_12 AB4 VDDA_12 AB6 GFX_RX15N AB7 GFX_RX15P AB9 GPP_RX3P AC1 GFX_TX14N AC10 VSSA AC11 VDDA_12_PKG AC12 VDDR AC13 DEBUG2 AC14 VSS AC15 VSS AC16 VSS AC17 DEBUG9 AC18 VDD_HT AC19 VDD_HT AC2 VSSA AC20 VDD_HT AC21 HT_RXCAD10P AC22 VSS AC23 VSS AC24 HT_RXCAD0P AC25 HT_RXCAD0N AC3 VDDA_12 AC4 VSSA AC5 VSSA AC6 VSSA AC7 VSSA AC8 SB_TX1P AC9 VSSA ...

Page 93: ...L3P D19 COMP D2 VDDA_12 D20 VDD_CORE D22 VDD_HT_PKG D23 VSS D24 HT_TXCALN D25 VSS D3 VDDA_12 D4 VSS D6 DFT_GPIO0 D7 DFT_GPIO1 D9 VDD_CORE E1 GFX_CLKN E11 VDDR3 E12 LVDS_DIGON E14 LPVSS E15 TXCLK_LP E17 TXOUT_L3N E19 RED E2 VDDA_12 E23 HT_TXCAD1P E24 HT_TXCAD0P E25 HT_TXCAD0N E3 VDDA_12 E6 VDDA_12 E7 VDD_PLL E9 VSS F1 VSSA F11 VSS F12 LVDS_BLEN F14 LVSSR F15 LVSSR F17 VSS F19 GREEN F2 GFX_CLKP Ball...

Page 94: ..._RX6P M5 GFX_RX6N M6 VSSA M7 GFX_RX5N M8 GFX_RX5P M9 VDDA_12 N1 GFX_TX4N N11 VDD_CORE N12 VSS N13 VDD_CORE N14 VSS N15 VDD_CORE N2 GFX_TX4P N23 HT_TXCTLP N24 HT_TXCAD7P N25 HT_TXCAD7N N3 VSSA P1 GFX_TX5N P11 VSS P12 VDD_CORE P13 VSS P14 VDD_CORE P15 VSS P17 VDD_CORE P18 HT_TXCAD14P P19 HT_TXCAD14N P2 GFX_TX5P P20 VSS P21 HT_TXCAD15P P22 HT_TXCAD15N P23 HT_TXCTLN P24 HT_RXCTLP P25 HT_RXCTLN P3 GFX_...

Page 95: ...GFX_RX14P W1 GFX_TX11P W11 SB_RX2P W12 SB_RX2N W14 SB_RX0P W15 SB_RX0N W17 VDD_HT W19 HT_RXCAD11P W2 GFX_TX11N W20 HT_RXCAD11N W21 HT_RXCLK1P W22 HT_RXCLK1N W23 VSS W24 VSS W25 HT_RXCLK0N W3 GFX_TX10N W4 GFX_RX12P W5 GFX_RX12N W6 VSSA W7 VDDA_12 W9 GFX_RX14N Y1 VSSA Y11 VSSA Y12 VSSA Y14 VSSA Y15 VSSA Y17 VDD_HT Y19 HT_RXCAD8N Y2 GFX_TX12P Y22 VSS Ball Ref Pin Name Y23 VSS Y24 HT_RXCLK0P Y25 VSS Y...

Page 96: ...X_RX4P L4 GFX_RX5N M7 GFX_RX5P M8 GFX_RX6N M5 GFX_RX6P M4 GFX_RX7N P7 GFX_RX7P P8 GFX_RX8N P5 GFX_RX8P P4 GFX_RX9N R5 GFX_RX9P R4 GFX_TX0N H2 GFX_TX0P J1 GFX_TX10N W3 GFX_TX10P V3 GFX_TX11N W2 GFX_TX11P W1 GFX_TX12N AA1 GFX_TX12P Y2 GFX_TX13N AB2 GFX_TX13P AA2 GFX_TX14N AC1 GFX_TX14P AB1 GFX_TX15N AE4 GFX_TX15P AE3 GFX_TX1N K1 GFX_TX1P K2 GFX_TX2N L3 GFX_TX2P K3 GFX_TX3N L2 GFX_TX3P L1 GFX_TX4N N1...

Page 97: ... HT_TXCAD8P F21 HT_TXCAD9N J21 HT_TXCAD9P J20 HT_TXCALN D24 HT_TXCALP C25 HT_TXCLK0N J25 HT_TXCLK0P J24 HT_TXCLK1N L22 HT_TXCLK1P L21 HT_TXCTLN P23 HT_TXCTLP N23 HTPVDD B24 HTPVSS B25 HTREFCLK B23 HTTSTCLK C23 I2C_CLK A2 I2C_DATA B4 LDTSTOP C5 LPVDD D14 LPVSS E14 LVDDR18D A12 LVDDR18D B12 LVDDR33 C12 LVDDR33 C13 LVDS_BLEN F12 LVDS_BLON G12 LVDS_DIGON E12 LVSSR A14 LVSSR A16 LVSSR C15 LVSSR C16 LVS...

Page 98: ...D_HT AD23 VDD_HT AD24 VDD_HT AE23 VDD_HT AE24 VDD_HT AE25 VDD_HT W17 VDD_HT Y17 VDD_HT_PKG D22 VDD_PLL E7 VDD_PLL F7 VDDA_12 AB3 VDDA_12 AB4 VDDA_12 AC3 VDDA_12 AD2 VDDA_12 AE1 VDDA_12 AE2 VDDA_12 B1 VDDA_12 C1 VDDA_12 D1 VDDA_12 D2 VDDA_12 D3 VDDA_12 E2 VDDA_12 E3 VDDA_12 E6 VDDA_12 F4 VDDA_12 G7 VDDA_12 L9 VDDA_12 M9 VDDA_12 U7 VDDA_12 W7 VDDA_12_PKG AC11 VDDA_12_PKG M1 VDDR AC12 VDDR AD12 VDDR ...

Page 99: ...C7 VSSA AC9 VSSA AD1 VSSA AD3 VSSA AE10 VSSA AE6 VSSA F1 Pin Name Ball Ref VSSA F3 VSSA G3 VSSA G6 VSSA H1 VSSA H3 VSSA J2 VSSA J3 VSSA J6 VSSA L6 VSSA M2 VSSA M3 VSSA M6 VSSA N3 VSSA P6 VSSA P9 VSSA R6 VSSA R9 VSSA T1 VSSA T3 Pin Name Ball Ref VSSA U2 VSSA U3 VSSA U6 VSSA V11 VSSA V12 VSSA V14 VSSA V15 VSSA W6 VSSA Y1 VSSA Y11 VSSA Y12 VSSA Y14 VSSA Y15 VSSA Y3 VSSA Y9 Y C20 Pin Name Ball Ref ...

Page 100: ... AB20 HT_RXCAD9P AB22 HT_RXCAD10N AB23 HT_RXCAD2P AB24 HT_RXCAD1P AB25 HT_RXCAD1N AB3 VDDA_12 AB4 VDDA_12 AB6 SB_RX0N AB7 SB_RX0P AB9 VDD_MEM AC1 SB_TX0P AC10 VSS AC11 MEM_BA0 AC12 VSS AC13 MEM_DQ2 AC14 MEM_WE AC15 MEM_DQ4 AC16 MEM_DM0 AC17 MEM_DQ9 AC18 VSS AC19 MEM_DQ12 AC2 SB_TX0N AC20 MEM_DQS1N AC21 HT_RXCAD10P AC22 VSS AC23 VSS AC24 HT_RXCAD0P AC25 HT_RXCAD0N AC3 VDDA_12 AC4 NC AC5 VDDA_12 AC6...

Page 101: ...25 HT_TXCALP C3 TESTMODE C4 VSS C5 LDTSTOP C6 DACVSYNC C7 DFT_GPIO3 C8 DFT_GPIO2 C9 VDD_CORE D1 VDDA_12 D11 VDDR3 D12 LVSSR D14 LPVDD D15 TXCLK_LN D17 TXOUT_L3P D19 COMP D2 VDDA_12 D20 VDD_CORE D22 VDD_HT_PKG D23 VSS D24 HT_TXCALN D25 VSS D3 VDDA_12 D4 VSS D6 DFT_GPIO0 D7 DFT_GPIO1 D9 VDD_CORE E1 GFX_CLKN E11 VDDR3 E12 LVDS_DIGON E14 LPVSS E15 TXCLK_LP E17 TXOUT_L3N E19 RED E2 VDDA_12 Ball Ref Pin...

Page 102: ...FX_RX4P L5 GFX_RX4N L6 VSSA L7 GFX_RX3N L8 GFX_RX3P L9 VDDA_12 M1 VDDA_12_PKG M11 VSS M12 VDD_CORE M13 VSS M14 VDD_CORE M15 VSS M17 VSS M18 HT_TXCAD12P M19 HT_TXCAD12N M2 VSSA M20 VSS M21 HT_TXCAD13N M22 HT_TXCAD13P M23 VSS M24 HT_TXCAD6N M25 VSS M3 VSSA M4 GFX_RX6P M5 GFX_RX6N M6 VSSA M7 GFX_RX5N M8 GFX_RX5P M9 VDDA_12 N1 GFX_TX4N N11 VDD_CORE N12 VSS N13 VDD_CORE N14 VSS Ball Ref Pin Name N15 VD...

Page 103: ...U4 GPP_RX1P U5 GPP_RX1N U6 VSSA U7 VDDA_12 V1 GPP_TX3N V11 VSS V12 MEM_CS V14 VSS V15 MEM_CKN V2 GPP_TX3P V23 HT_RXCAD5P V24 HT_RXCAD4P V25 HT_RXCAD4N V3 GPP_TX0P Ball Ref Pin Name V9 SB_RX1P W1 GPP_TX1P W11 MEM_COMPN W12 MEM_A0 W14 MEM_A4 W15 MEM_CKP W17 VSS W19 HT_RXCAD11P W2 GPP_TX1N W20 HT_RXCAD11N W21 HT_RXCLK1P W22 HT_RXCLK1N W23 VSS W24 VSS W25 HT_RXCLK0N W3 GPP_TX0N W4 SB_RX3P W5 SB_RX3N W...

Page 104: ...GFX_TX6P P3 GFX_TX7N R2 GFX_TX7P R1 GPP_RX0N R8 GPP_RX0P R7 GPP_RX1N U5 GPP_RX1P U4 GPP_RX2N P5 GPP_RX2P P4 GPP_RX3N R5 GPP_RX3P R4 GPP_TX0N W3 GPP_TX0P V3 GPP_TX1N W2 GPP_TX1P W1 GPP_TX2N U1 GPP_TX2P U2 GPP_TX3N V1 GPP_TX3P V2 GREEN F19 HT_RXCAD0N AC25 HT_RXCAD0P AC24 HT_RXCAD10N AB22 HT_RXCAD10P AC21 HT_RXCAD11N W20 HT_RXCAD11P W19 HT_RXCAD12N U19 Pin Name Ball Ref HT_RXCAD12P U18 HT_RXCAD13N U2...

Page 105: ...ON G12 LVDS_DIGON E12 LVSSR A14 LVSSR A16 LVSSR C15 LVSSR C16 LVSSR C19 LVSSR D12 LVSSR F14 LVSSR F15 MEM_A0 W12 MEM_A1 AD10 MEM_A10 AE10 MEM_A11 Y14 MEM_A12 AD9 MEM_A13 AA11 MEM_A2 AB12 MEM_A3 AB11 MEM_A4 W14 MEM_A5 AB15 MEM_A6 AB14 MEM_A7 AE9 MEM_A8 AA12 MEM_A9 AC9 MEM_BA0 AC11 MEM_BA1 AE11 MEM_BA2 AD11 MEM_CAS Y15 MEM_CKE AD12 MEM_CKN V15 MEM_CKP W15 MEM_COMPN W11 MEM_COMPP Y11 MEM_CS V12 MEM_D...

Page 106: ...ORE J19 VDD_CORE L11 VDD_CORE L13 VDD_CORE L15 VDD_CORE L17 VDD_CORE M12 VDD_CORE M14 VDD_CORE N11 VDD_CORE N13 VDD_CORE N15 VDD_CORE P12 VDD_CORE P14 VDD_CORE P17 VDD_CORE R11 VDD_CORE R13 VDD_CORE R15 VDD_CORE U11 VDD_CORE U12 VDD_CORE U14 VDD_CORE U15 VDD_HT AD22 VDD_HT AD23 VDD_HT AD24 VDD_HT AE22 VDD_HT AE23 VDD_HT AE24 VDD_HT AE25 VDD_HT_PKG D22 VDD_MEM AA9 VDD_MEM AB9 VDD_MEM AC7 VDD_MEM AC...

Page 107: ...13 VSS P15 VSS P20 VSS R12 VSS R14 VSS R17 VSS R20 VSS R23 VSS R24 VSS T23 VSS T25 VSS U20 VSS V11 VSS V14 VSS W17 VSS W23 VSS W24 VSS Y12 Pin Name Ball Ref VSS Y22 VSS Y23 VSS Y25 VSS_PLL F9 VSS_PLL G9 VSSA A1 VSSA AA3 VSSA AA7 VSSA AC6 VSSA AD1 VSSA AE1 VSSA F1 VSSA F3 VSSA G3 VSSA G6 VSSA H1 VSSA H3 VSSA J2 VSSA J3 VSSA J6 VSSA L6 VSSA M2 VSSA M3 VSSA M6 VSSA N3 VSSA P6 VSSA P9 VSSA R6 VSSA R9 ...

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Page 109: ...fied and distinguished from the RS690T by an e fuse on the chip There are no identification registers that differentiate the two devices A TV Output The RS690T provides SDTV PAL or NTSC standard with composite S Video separate luminance and chrominance channels or YCbCr 480i YUV standard definition component output and HDTV YPbPr 480i 480p 576i 576p 720p 1080i outputs through the on chip DACs that...

Page 110: ...The minimum version number for the LVDS output is 10 55 0 15 and for the TMDS DVI output is 10 55 0 31 Contact your AMD CSS representative for the latest video BIOS A custom video BIOS and proper signal routing from the LVTM interface to a DVI connector are the only requirements for the RS690E to support a TMDS DVI output on the LVTM interface No other register programming is needed Users should n...

Page 111: ...alog Output on the DVI I Connector below Figure B 4 Pins for Analog Output on the DVI I Connector For the single link DVI output portion of the DVI I connector AMD recommends using the RS690E s LVTM interface to provide the DVI output and routing these digital signals see Figure B 3 RS690E LVTM Interface to the appropriate inputs on the DVI I connector The video BIOS must be configured so that the...

Page 112: ... the RS690E s TMDS interface that is multiplexed on its PCI E graphics lanes can also enable HDMI single link only Note The TMDS interface multiplexed on the PCI E graphics lanes cannot enable HDMI when the LVTM interface is supporting HDMI and vice versa B 5 HDCP The RS690E supports HDCP on data streams for single link transmission with on chip key storage It is available either on the DVI HDMI d...

Page 113: ...al Description TXOUT_L0N TX0M O LVDDR33 LVDDR18D VSSLT None TMDS data channel 0 TXOUT_L0P TX0P O LVDDR33 LVDDR18D VSSLT None TMDS data channel 0 HD Audio SW Frame Buffers A B Live in memory Mux LVDS TMDS LVTM Interface PCI E x8 TMDS PCI E TMDS Interface DAC CRT Interface SW SW SW LVDS Output or TMDS output TMDS output or PCI E GFX Signals CRT Output Notes 1 Each switch represents 2 possible config...

Page 114: ... The channel is only used in DVI dual link mode and is not used for HDMI support NC if unused TXOUT_U0P TX4P O LVDDR33 LVDDR18D VSSLT None TMDS data channel 4 The channel is only used in DVI dual link mode and is not used for HDMI support NC if unused TXOUT_U1N TX5M O LVDDR33 LVDDR18D VSSLT None TMDS data channel 5 The channel is only used in DVI dual link mode and is not used for HDMI support NC ...

Page 115: ...nging 15 2VSW VUS Differential Output Undershoot Ringing 25 2VSW IDDLP Average Supply Current at LPVDD 20 0 mA 2 IDDLV Average Supply Current at LVDDR18D and LVDDR33 100 0 mA 2 IPDLP Power Down Current at LPVDD 10 0 µA 3 IPDLV Power Down Current at LVDDR18D and LVDDR33 10 0 µA 3 Notes 1 AVCC stands for the termination supply voltage of the receiver which is 3 3V 5 2 Measured under typical conditio...

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Page 117: ... Reflow Process Recommendations Removed information on eutectic solder as it is irrelevant Updated Table 6 2 ACPI Signal Definitions Removed SUS_STAT from SB form the table Updated Table 7 4 2 VOH VOL Tree Activation Corrected instruction in step 10 to 0101 1101 Rev0 3 Aug 2006 Added references to the RS690MC Added legal disclaimers concerning DVI and HDMI references in this book Updated Section 1...

Page 118: ...for RS690T to support a x8 general purpose device on the PCI E graphics interface Added Section 1 5 3 ATI HyperMemory Technology Updated Section 1 5 9 Multiple Display Features Corrected TV modes supported Added Section 1 7 2 Branding Diagrams for ASIC Revision A12 and After Moved LVDS Spread Spectrum section from Section 2 4 1 to Section 2 3 2 Updated Table 3 7 Clock Interface revised description...

Page 119: ...tures Corrected the registers by which the LCD panel power up down timing is programmed Section 4 8 LCD Panel Power Up Down Timing Removed support for ACPI S1 state Section 1 5 12 Power Management Features and Section 6 1 ACPI Power Management Implementation Updated the solder reflow profile Section 5 3 3 2 Reflow Profile Rev 3 05 Oct 2007 Added information on the RS690E Appendix B AMD RS690E Rev ...

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