VOH/VOL Test
© 2008 Advanced Micro Devices, Inc.
41978 AMD RS690M Databook 3.06
Proprietary
7-7
8. Load JTAG instruction register with the instruction 1001 1001.
9. Run test by loading JTAG data register with data 0000 0000 0000 00xy, where bit x is the input value for
TEST_ODD and bit y that for TEST_EVEN (see Table 7-5 above).
10. To end test, load JTAG instruction register with the instruction 0101 1101.
7.4.3
VOH/VOL Pin List
Table 7-6 and Table 7-7 below show the RS690M and the RS690T VOH/VOL trees. There is no specific order of
connection. Under the Control column, an “ODD” or “EVEN” indicates that the logical output of the pin is same as the
“TEST_ODD” or “TEST_EVEN” input respectively.
When a differential pair appear in the table as a single entry, the output of the positive (“P”) pin is indicated in the Control
column (see last paragraph for explanations), and the output of the negative pin (“N”) will be of the opposite value. E.g.,
for entry no. 1 on the tree, when TEST_EVEN is 1, HT_TXCAD15P will give a value of 1 and HT_TXCAD15N will give
a value of 0.
Table 7-6 RS690M VOH/VOL Tree
No.
Pin Name
Ball Ref.
Control
1
HT_TXCAD15P/N
P21/P22
EVEN
2
HT_TXCAD14P/N
P18/P19
ODD
3
HT_TXCAD13P/N
M22/M21
EVEN
4
HT_TXCAD12P/N
M18/M19
ODD
5
HT_TXCAD11P/N
L18/L19
EVEN
6
HT_TXCAD10P/N
G22/G21
ODD
7
HT_TXCAD9P/N
J20/J21
EVEN
8
HT_TXCAD8P/N
F21/F22
ODD
9
HT_TXCTLP/N
N23/P23
EVEN
10
HT_TXCAD7P/N
N24/N25
ODD
11
HT_TXCAD6P/N
L25/M24
EVEN
12
HT_TXCAD5P/N
K25/K24
ODD
13
HT_TXCAD4P/N
J23/K23
EVEN
14
HT_TXCAD3P/N
G25/H24
ODD
15
HT_TXCAD2P/N
F25/F24
EVEN
16
HT_TXCAD1P/N
E23/F23
ODD
17
HT_TXCAD0P/N
E24/E25
EVEN
18
DACSCL
B6
ODD
19
DACVSYNC
C6
EVEN
20
DACHSYNC
A5
ODD
21
LVDS_BLON
G12
EVEN
22
LVDS_BLEN
F12
ODD
23
LVDS_DIGON
E12
EVEN
24
DFT_GPIO5
A8
ODD
25
DFT_GPIO4
B8
EVEN
26
DFT_GPIO3
C7
ODD
27
DFT_GPIO2
C8
EVEN
28
DFT_GPIO1
D7
ODD
29
DFT_GPIO0
D6
EVEN
30
SB_TX3P/N
AD7/AE7
ODD
31
SB_TX2P/N
AD8/AE8
EVEN
32
SB_TX1P/N
AC8/AD9
ODD
33
SB_TX0P/N
AE9/AD10
EVEN
34
GPP_TX3P/N
AD5/AD6
ODD
35
GPP_TX2P/N
AD4/AE5
EVEN
36
GPP_TX1P/N
AD19/AE19
ODD
37
GPP_TX0P/N
AD14/AD15
EVEN
38
GFX_TX15P/N
AE3/AE4
ODD
39
GFX_TX14P/N
AB1/AC1
EVEN
40
GFX_TX13P/N
AA2/AB2
ODD
41
GFX_TX12P/N
Y2/AA1
EVEN
42
GFX_TX11P/N
W1/W2
ODD
43
GFX_TX10P/N
V3/W3
EVEN
44
GFX_TX9P/N
V2/V1
ODD
45
GFX_TX8P/N
T2/U1
EVEN
46
GFX_TX7P/N
R1/R2
ODD
47
GFX_TX6P/N
P3/R3
EVEN
48
GFX_TX5P/N
P2/P1
ODD
No.
Pin Name
Ball Ref.
Control