AMD RS690M, Technical Reference Manual

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41978 AMD RS690M Databook 3.06 © 2008 Advanced Micro Devices, Inc.
4-2 Proprietary
LVDS Timing
The fraction of strobe delay, in terms of a memory clock period is (24+MCA_DLL_ADJ_DQSR) / 240. For example: if
MCA_DLL_ADJ_DQSR_1 = 36, then DQS1 is delayed by 0.25 x memory_clock_period. So, if the memory clock period
is 5ns, then DQS1 is delayed internally by 1.25ns with respect to DQ[15:8].
4.4.2 Write Cycle DQ/DQS Delay
Similar to a read cycle, during memory write cycle there is a DLL inside the RS690T that can delay each DQS signal with
respect to its byte of the DQ valid window. This delay ensures adequate setup and hold time for DQ and DQS to the
memory. This DLL delay is programmable by the following registers in the same manner as with the read cycle:
MCA_DLL_SLAVE_WR_0.MCA_DLL_ADJ_DQ_B0 <NBMCIND : 0xE8[7:0]>
MCA_DLL_SLAVE_WR_1.MCA_DLL_ADJ_DQ_B1 <NBMCIND : 0xE9[7:0]>
Again, the fraction of strobe delay, in terms of a memory clock period is (24+MCA_DLL_ADJ_DQSR) / 240. For
example: if MCA_DLL_ADJ_DQ_B0 = 96, then DQS0 is delayed by 0.5 x memory_clock_period. So, if the memory
clock period is 5ns, then DQS0 is delayed internally by 2.5ns with respect to DQ[7:0].
Depending on the board layout of DQS and DQ signals, it may be necessary to have different delays for each DQS signal.
Layouts of the DQS and DQ signals should follow the rules given in the
RS690/RS485-Series IGP Motherboard Design
Guide.
4.5 LVDS Timing
4.6 OSCIN Timing
Table 4-3 Timing Requirements for the LVDS Interface
Parameter Min Typ Max Unit Notes
Differential Clock Period 11.7 – 40 ns 1
Differential Clock Frequency 25 – 85 MHz
Frequency of the LVDS PLL VOC 175 – 595 MHz
Differential Clock Cycle-to-Cycle Jitter – – 420 ps 1
Transmitter PLL Reset Time 10 – –
µ
s
1,2
Transmitter PLL Lock Time
– – 750
µ
s 1,3
Differential Low-to-High Transition Time
0.26 –
0.3T
b
ns 4
Differential High-to-Low Transition Time
0.26 –
0.3T
b
ns 4
Data Channel to Channel Skew – 100 – ps
Notes:
1 Time intervals measured at 50% LTPVDD18 threshold point.
2 Minimum time to keep LVDS_PLL_RESET asserted.
3 Measured after LVDS_PLL_RESET is de-asserted.
4 T
b
is the bit-time, which is 1/7 of the differential clock period.
Table 4-4 Timing Requirements for the OSCIN Pad
Symbol Parameter Min Typical Max Unit Note
TIP REFCLK Period 0.037 – 1.1
µ
s 1
FIP REFCLK Frequency 0.9 – 27 MHz 2
TIR REFCLK Rise Time – – 1.5 ns
TIF REFCLK Fall Time – – 1.5 ns