© 2008 Advanced Micro Devices, Inc.
41978 AMD RS690M Databook 3.06
Proprietary
7-1
Chapter 7
Testability
7.1
Test Capability Features
The RS690M has integrated test modes and capabilities. These test features cover both the ASIC and board level testing.
The ASIC tests provide a very high fault coverage and low DPM (Defect Per Million) ratio of the part. The board level
tests modes can be used for motherboard manufacturing and debug purposes. The following are the test modes of the
RS690M:
•
Full scan implementation on the digital core logic that provides about 99% fault coverage through ATPG (Automatic
Test Pattern Generation Vectors).
•
Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules.
•
Improved access to the analog modules and PLLs in the RS690M to allow full evaluation and characterization of
these modules.
•
A JTAG test mode (which is not entirely compliant to the IEEE 1149.1 standard) to allow board level testing of
neighboring devices.
•
An XOR TREE test mode on all the digital I/Os to allow for proper soldering verification at the board level.
•
A VOH/VOL test mode on all digital I/Os to allow for proper verification of output high and output low voltages at
the board level.
These test modes can be accessed through the settings on the instruction register of the JTAG circuitry.
7.2
Test Interface
7.3
XOR Tree
7.3.1
Brief Description of an XOR Tree
An example of a generic XOR tree is shown in the
below.
Table 7-1
Pins on the Test Interface
Pin Name
Ball number
Type
Description
TESTMODE
C3
I
IEEE 1149.1 test port reset
DDC_DATA
B3
I
TMS: Test Mode Select (IEEE 1149.1 test mode select)
I2C_DATA
B4
I
TDI: Test Mode Data In (IEEE 1149.1 data in)
I2C_CLK
A2
I
TCLK: Test Mode Clock (IEEE 1149.1 clock)
TMDS_HPD
C14
O
TDO: Test Mode Data Out (IEEE 1149.1 data out)
POWERGOOD
C11
I
I/O Reset
OSCIN
B11
I
I/O Test Clock
