41978 AMD RS690M Databook 3.06
© 2008 Advanced Micro Devices, Inc.
4-4
Proprietary
Power Rail Power Up Sequence
4.7
Power Rail Power Up Sequence
Figure 4-1 Power Rail Power Up Sequence for the RS690M
Table 4-5 RS690M Power Rail Power Up Sequence Requirements
Figure 4-1 above only shows the power up sequence for the power rails that the RS690M connects to. For a power up
sequence for the whole RS690M platform, please refer to the
RS690/RS485-Series IGP Motherboard Design Guide
.
Symbol
Parameter
Voltage Difference During Ramping
Minimum (V)
Maximum (V)
T11
3.3V rails ramp high relative to 1.8V
display and PLL rails
0
2.1
T12
1.8V memory (RS690T only) and debug
I/O rail ramps high relative to VDD_CORE
(1.2V)
0
No restrictions
T13
1.8V display and PLL rails ramp high
relative to 1.2V PLL rails
0
No restrictions
T14
1.2V PLL rails ramp high relative to
VDD_CORE (1.2V)
0
No restrictions
Notes:
1.
Power rails in the same group may require separate power sources. Please refer to the
RS690/RS485-series IGP
Motherboard Design Guide
for details.
2. There are no specific requirements for the following 1.2V rails: VDD_HT, VDDA_12, and VDD_PLL.
3. For power down, the rails should either be turned off simultaneously or in the reversed order of the above power up
sequence. Variations in speeds of decay due to different capacitor discharge rates can be safely ignored.
T11
T13
T14
1.8V Memory and
Debug I/O Rails
(VDD_MEM*, VDDR**)
T12
3.3V Rails
(VDDR3, LVDDR33, AVDD)
1.8V Display and PLL Rails
(PLLVDD18, IOPLLVDD18*,
LVDDR18D, LPVDD, AVDDDI,
AVDDQ, HTPVDD, VDD_18)
1.2V PLL Rails
(PLLVDD12, IOPLLVDD12*)
1.2V VDD_CORE
Notes:
* RS690T Only
** RS690M only
