SERIES IP511 INDUSTRIAL I/O PACK ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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The communication cabling of the P2 interface carries digital data
at a high transfer rate. For best performance, increased signal integrity,
and safety reasons, you should isolate these connections away from
power and other wiring to avoid noise-coupling and crosstalk
interference. EIA/TIA-422B communication distances are generally
limited to less than 4000 feet. Always keep interface cabling and
ground wiring as short as possible for best performance. Please refer
to Drawing 4501-580 for example connections and recommended
grounding practices.
Note that rapidly changing isolation-mode voltages (voltage across
the isolation barrier) can cause data errors by causing the receiver
output to change states. As the rate of change of isolation mode
voltages increases, an increase in data errors will occur. Approximately
half of the IP511 modules will experience data errors with isolation
mode voltage transients of 1.6KV/us. Some errors may be encountered
with isolation-mode transients down to 500V/us. To help put this into
perspective, a 1000Vrms, 60Hz, isolation mode voltage has a rate of
change of only 0.5V/us and would never be a problem. But if you
should experience data errors while operating in isolated mode, then
some thought should be given to preventing the port power supplies
from floating by referencing them to earth ground. In any case, after a
data error is encountered, a channel will recover and subsequent
changes in input data will produce correct output data.
IP Logic Interface Connector (P1)
Table 2.2: Standard Logic Interface Connections (P1)
Pin Description
Number
Pin Description
Number
GND
1
GND
26
CLK
2
+5V
27
Reset*
3
R/W*
28
D00
4
IDSEL*
29
D01
5
DMAReq0*
30
D02
6
MEMSEL*
31
D03
7
DMAReq1*
32
D04
8
IntSel*
33
D05
9
DMAck0*
34
D06
10
IOSEL*
35
D07
11
RESERVED
36
D08
12
A1
37
D09
13
DMAEnd*
38
D10
14
A2
39
D11
15
ERROR*
40
D12
16
A3
41
D13
17
INTReq0*
42
D14
18
A4
43
D15
19
INTReq1*
44
BS0*
20
A5
45
BS1*
21
STROBE*
46
-12V
22
A6
47
+12V
23
ACK*
48
+5V
24
RESERVED
49
GND
25
GND
50
An Asterisk (*) is used to indicate an active-low signal.
BOLD ITALIC
Logic Lines are NOT USED by this IP Model.
P1 of the IP module provides the logic interface to the mating
connector on the carrier board. This connector is a 50-pin female
receptacle header (AMP 173279-3 or equivalent) which mates to the
male connector of the carrier board (AMP 173280-3 or equivalent).
This provides excellent connection integrity and utilizes gold-plating in
the mating area. Threaded metric M2 screws and spacers are supplied
with the IP module to provide additional stability for harsh environments
(see Drawing 4501-434 for assembly details). Field and logic side
connectors are keyed to avoid incorrect assembly. The pin
assignments of P1 are standard for all IP modules according to the
Industrial I/O Pack Specification (see Table 2.2).
3.0 PROGRAMMING INFORMATION
ADDRESS MAPS
This board is addressable in the Industrial Pack I/O space to
control the interface configuration, data transfer, and steering logic of
four EIA/TIA-422B serial ports. As such, three types of information are
stored in the I/O space: control, status, and data. These registers are
listed below along with their mnemonics used throughout this manual.
IP511 Data, Status, & Control Registers
SERIAL DATA REGISTERS (Per Serial Port):
RBR
Receive Buffer Register
THR
Transmitter Holding Register
SERIAL STATUS REGISTERS (Per Serial Port):
LSR
Line Status Register
MSR
Modem Status Register
SERIAL CONTROL REGISTERS (Per Serial Port):
LCR
Line Control Register
FCR
FIFO Control Register
MCR
Modem Control Register
DLL
Divisor Latch LSB
DLM
Divisor Latch MSB
IER
Interrupt Enable Register
SCR
Scratchpad/Interrupt Vector Register
EFR
Enhanced Feature Register (IP511-64 Models)
XON-1
XON-1 Word (IP511-64 Models Only)
XON-2
XON-2 Word (IP511-64 Models Only)
XOFF-1
XOFF-1 Word (IP511-64 Models Only)
XOFF-2
XOFF-2 Word (IP511-64 Models Only)
Shaded register entries apply to Model IP511-64 only and are
accessible after writing “BF” to the Line Control Register (LCR).
The I/O space may be as large as 64, 16-bit words (128 bytes)
using address lines A1..A6, but the IP511 uses only a portion of this
space. The I/O space address map for the IP511 is shown in Table 3.1
(shaded registers apply to IP511-64 models only). Note the base
address for the IP module I/O space (see your carrier board
instructions) must be added to the addresses shown to properly access
the I/O space. All accesses are performed on an 8-bit word basis
(D0..D7).
This manual is presented using the “Big Endian” byte ordering
format. Big Endian is the convention used in the Motorola 68000
microprocessor family and is the VMEbus convention. In Big Endian,
the lower-order byte is stored at odd-byte addresses. Thus, byte
accesses are done on odd address locations. The Intel x86 family of
microprocessors use the opposite convention, or “Little Endian” byte
ordering. Little Endian uses even-byte addresses to store the low-order
byte. As such, use of this module on an ISAbus (PC/AT) carrier board
will require the use of the even address locations to access the 8-bit
data, while a VMEbus carrier will require the use of odd address
locations.
