SERIES IP511 INDUSTRIAL I/O PACK ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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Table 3.2: Baud Rate Divisors and Relative Error (8MHz Clk)
BAUD RATE
DESIRED
DIVISOR (N) USED
FOR 16x CLOCK
% ERROR DIFF BET
DESIRED & ACTUAL
50
10000
2710H
0
75
6667
1A06H
0.005
110
4545
11C1H
0.010
134.5
3717
0E85H
0.013
150
3333
0D05H
0.010
300
1667
0683H
0.020
600
833
0341H
0.040
1200
417
01A1H
0.080
1800
277
0115H
0.080
2000
250
00FAH
0
2400
208
00D0H
0.160
3600
139
0086H
0.080
4800
104
0068H
0.160
7200
69
0045H
0.644
9600
52
0034H
0.160
19200
26
001AH
0.160
38400
13
000DH
0.160
56000
9
0009H
0.790
128000
4
0004H
2.344
256000
2
0002H
2.344
512000
1
0001H
2.400
With respect to this device, the baud rate may be considered equal
to the number of bits transmitted per second (bps). The bit rate (bps),
or baud rate, defines the bit time. This is the length of time a bit will be
held on before the next bit is transmitted. A receiver and transmitter
must be communicating at the same bit rate, or data will be garbled. A
receiver is alerted to an incoming character by the start bit, which marks
the beginning of the character. It then times the incoming signal,
sampling each bit as near to the center of the bit time as possible.
To better understand the asynchronous timing used by this device,
note that the receive data line (RxD) is monitored for a high-to-low
transition (start bit). When the start bit is detected, a counter is reset
and counts the 16x sampling clock to 7-1/2 (which is the center of the
start bit). The receiver then counts from 0 to 15 to sample the next bit
near its center, and so on, until a stop bit is detected, signaling the end
of the data stream.
Use of a sampling rate 16x the baud rate reduces the
synchronization error that builds up in estimating the center of each
successive bit following the start bit. As such, if the data on RxD is a
symmetrical square wave, the center of each successive data cell will
occur within
±
3.125% of the actual center (this is 50%
÷
16, providing
an error margin of 46.875%). Thus, the start bit can begin as much as
one 16x clock cycle prior to being detected.
EFR - Enhanced Function Register, Ports A-D (R/W)
(Model IP511-64 Only)
The enhanced features of the Model IP511-64 can be
enabled/disabled via this register. This register is also used to unlock
access to programming the extended register functionality of IER bits 4-
7, IIR bits 4-5, FCR bits 4-5, and MCR bits 5-7. It is also used to
program software flow control. Note that bits 6 & 7 are used for
hardware flow control, but the handshake lines RTS & CTS are not
implemented on this model and bits 6 & 7 should be programmed to 0.
Enhanced Function Register (EFR)
EFR BIT
FUNCTION
0-3
Allows combinations of software flow control to be
programmed (see table below).
4
Enhanced Functions Enable bit.
0 = disable enhanced functions controlled via IER bits
4-7, IIR bits 4-5, FCR bits 4-5, and MCR bits 5-7
(Note that after reset, these bits are set to “0” to
manintain compatibility with the 16C550 standard
functionality mode).
1 = Enable all enhanced features. Allows IER bits 4-7,
IIR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be
modified. Then after modification, EFR bit 4 can be
set to “0” to latch the contents, and prevent existing
software from overwriting the enhanced functionality
provided by these bits.
5
0 = Normal;
1 = Enable Special Character Detect. If enabled, the
UART will compare the received data with the XOFF-2
data. Upon a correct match, the received data will be
transferred to the FIFO and IIR bit 4 will be set to
indicate the detection of the special character.
6
Hardware RTS flow Control Enable (Not Supported)
0 = Normal (RTS flow control disabled);
1 = Enable RTS* pin to go high (deasserted) when the
receive FIFO has reached its programmed trigger level
(RTS* is not connected on Model IP511).
7
Hardware CTS flow Control Enable (Not Supported)
0 = Normal (CTS flow control disabled);
1 = Resume transmission when a low input signal is
detected on the CTS* pin (CTS* is not connected on
Model IP511).
Different conditions can be set to detect XON/XOFF characters in
the data stream, or start/stop transmission. The following table lists all
the possible conditions:
Software Flow Control Via EFR Bits 0-3
Bit3
Bit2
Bit1
Bit0
Tx/Rx Software Flow Controls
0
0
X
X
No Transmit Flow Control
1
0
X
X
Transmit XON1, XOFF1
0
1
X
X
Transmit XON2, XOFF2
1
1
X
X
Transmit XON1, XON2:
XOFF1, XOFF2
X
X
0
0
No Receive Flow Control
X
X
1
0
Receiver Compares XON1,XOFF1
X
X
0
1
Receiver Compares XON2,XOFF2
1
0
1
1
Transmit XON1, XOFF1. Receiver
Compares XON1 or XON2,
XOFF1 or XOFF2.
0
1
1
1
Transmit XON2, XOFF2. Receiver
Compares XON1 or XON2,
XOFF1 or XOFF2.
1
1
1
1
Transmit XON1 & XON2: XOFF1
& XOFF2. Receiver Compares
XON1 & XON2: XOFF1 & XOFF2.
0
0
1
1
No Transmit Flow Control.
Receiver Compares XON1 &
XON2: XOFF1 and XOFF2.
Note that access to this register is granted only after writing “BF” to
the Line Control Register (LCR). EFR Bits 0-7 are set to 0 upon power-
up or system reset.
