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Series IP511 Industrial I/O Pack

Isolated Quad EIA-422B Communication Module

USER’S MANUAL

ACROMAG INCORPORATED

30765 South Wixom Road

P.O. BOX 437

Wixom, MI 48393-7037 U.S.A.

Tel: (248) 624-1541

Fax: (248) 624-9234

Data and specifications are subject to change without notice.

8500-550-C98M015

Summary of Contents for IP511 Series

Page 1: ...tion Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1996 Acromag Inc Printed in the USA Data and spe...

Page 2: ...ystem This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acr...

Page 3: ...er Acromag IP modules are also available to serve your signal conditioning and interface needs Note Since all connections to field signals are made through the carrier board which passes them to the i...

Page 4: ...ive data paths This SIP can be easily removed or replaced if required see Drawing 4501 581 4501 582 Network Termination Bias Resistor Placement You need to consider your network application carefully...

Page 5: ...h To the communication network master this line pair is used as the transmit data path To the communication network slave this line pair comprises the receive data path Because a separate pair of line...

Page 6: ...ides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environ...

Page 7: ...Port A Line Control Register 07 08 Not Driven1 R W MCR Port A Modem Control Register 09 0A Not Driven1 R W LSR Port A Line Status Register 0B 0C Not Driven1 R W MSR Port A Modem Status Register 0D 0E...

Page 8: ...R W SCR Port C Scratch Pad Interrupt Vector Register 2F Shaded register entries apply to Model IP511 64 only and are accessible after writing BF to the Line Control Register LCR Table 3 1 IP511 I O Sp...

Page 9: ...g an invalid data character due to a low going noise spike on RxD If the data on RxD is a symmetrical square wave the center of the data cells will occur within 3 125 of the actual center providing an...

Page 10: ...extended register functionality of IER bits 4 7 IIR bits 4 5 FCR bits 4 5 and MCR bits 5 7 It is also used to program software flow control Note that bits 6 7 are used for hardware flow control but th...

Page 11: ...7 NO FUNCTION FOR MODEL IP511 0 Disable the CTS interrupt 1 Enable the generation of the CTS interrupt when CTS changes from a low to high state The IP511 does not implement the CTS line and this bit...

Page 12: ...FO TRIGGER LEVEL 00 01 Bytes 08 Bytes for IP511 64 Models 01 04 Bytes 16 Bytes for IP511 64 Models 10 08 Bytes 56 Bytes for IP511 64 Models 11 14 Bytes 60 Bytes for IP511 64 Models LCR Line Control Re...

Page 13: ...the selected serial channel In Loopback Mode interrupts are generated by controlling the state of the four lower order MCR bits internally instead of by the external hardware paths However no interru...

Page 14: ...errupt a priority 1 interrupt in the IIR register when any one of these conditions are detected This interrupt is enabled by setting IER bit 2 to 1 A power up or system reset sets all LSR bits to 0 ex...

Page 15: ...Low Interrupt Modem Status Changes Read MSR Reset Low OUT1 Reset High OUT2 Reset High After a power up the isolation buffer s output is initialized high As a result the very first bit transmitted or...

Page 16: ...the FIFO drops below its trigger level When the receiver FIFO and receiver interrupts are enabled the following receiver FIFO character time out status conditions apply 1 A FIFO character time out int...

Page 17: ...oo quickly to be processed or buffered thus preventing the loss of excess data The flow control characters are stored in the XON 1 2 and XOFF 1 2 registers Two XON XOFF registers are provided because...

Page 18: ...functionality of the circuitry used on the board is also included Refer to the Block Diagram Drawing 4501 583 Interface Diagram Drawing 4501 581 and Interface Level Diagram Drawing 4501 584 as you re...

Page 19: ...nsmit the byte Two other parity formats not supported by this module are mark parity and space parity Mark parity specifies that the parity bit will always be a logical 1 space parity requires the par...

Page 20: ...ed isolated only when isolated external port power is provided to the port Optionally the port may use P1 power by programming the power and common jumpers appropriately In this mode the port is consi...

Page 21: ...o RFI No data upsets occur for field strengths up to 10V per meter at 27MHz 151MHz 460MHz per SAMA PMC 33 1 test procedures Resistance to EMI Unit has been tested with no data upsets under the influen...

Page 22: ...performance with precision analog I O applications Application Used to connect a Model 5025 552 termination panel to the AVME9630 9660 non intelligent carrier board A D connectors both have 50 pin con...

Page 23: ...r Boards Application This panel converts the high density ribbon cable connectors coming from the APC8600 carrier board Acromag cable Model 5029 900 to screw terminals for direct wired interfaces This...

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