SERIES IP511 INDUSTRIAL I/O PACK ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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A modem status interrupt (4th priority) will never occur for this
model since no handshake lines are provided. Bits 4 and 5 of this
register are always set to “0” on standard units. Bits 6 and 7 are set to
“1” when bit 0 of the FIFO Control Register is set to “1” (bits 6 & 7 are
“0” in 16C450 mode). A power-up or system reset sets IIR bit 0 to “1”,
bits 1-7 to “0”.
Interrupt Identification Register (Model IP511-64 Only)
BITS
5 - 4
INT
PRTY
INTERRUPT SOURCE
0
1
5
Received XOFF Signal/Special Character
1
0
6
CTS/RTS Change-of-State Detected
(NO FUNCTION FOR IP511)
Bits 4 & 5 are set to 0 on IP511-16 models.
FCR - FIFO Control Register, Ports A-D (WRITE Only)
This write-only register is used to enable and clear the FIFO
buffers, set the trigger level of the Rx FIFO, and select the type of DMA
signaling (DMA is NOT supported by this model). IP511-64 models
also allow the trigger level of the Tx FIFO to be set. A power-up or
system reset resets all FCR bits to “0”.
FIFO Control Register
FCR BIT
FUNCTION
0
When set to “1”, this bit enables both the Tx and Rx
FIFO’s. All bytes in both FIFO’s can be cleared by
resetting this bit to 0. Data is cleared automatically
from the FIFO’s when changing from FIFO mode to
the alternate (16C450) mode and visa-versa.
Programming of other FCR bits is enabled by setting
this bit to 1.
1
When set to “1”, this bit clears all bytes in the Rx-
FIFO and resets the counter logic to 0 (this does not
clear the shift register).
2
When set to “1”, this bit clears all bytes in the Tx-
FIFO and resets the counter logic to 0 (this does not
clear the shift register).
3
When set to “1”, this bit sets DMA Signal from Mode
0 to Mode 1, if FIFO Control Register Bit 0 = 1 (DMA
is Not Supported).
4,5
Not Used on IP511-16 Models.
(IP511-64 Only) Used for setting the trigger level of
the Tx FIFO interrupt as follows:
BIT 5-4 Tx-FIFO TRIGGER LEVEL
00 08 Bytes for IP511-64 Models
01 16 Bytes for IP511-64 Models
10 32 Bytes for IP511-64 Models
11 56 Bytes for IP511-64 Models
6,7
Used for setting the trigger level of the Rx FIFO
interrupt as follows:
BIT 7-6 Rx-FIFO TRIGGER LEVEL
00 01 Bytes /08 Bytes for IP511-64 Models
01 04 Bytes /16 Bytes for IP511-64 Models
10 08 Bytes /56 Bytes for IP511-64 Models
11 14 Bytes /60 Bytes for IP511-64 Models
LCR - Line Control Register, Ports A-D (Read/Write)
The individual bits of this register control the format of the data
character as follows:
Line Control Register
LCR Bit
FUNCTION
PROGRAMMING
1 and 0
Word
Length Sel
0 0 = 5 Data Bits
0 1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data Bits
2
Stop Bit
Select
0 = 1 Stop Bit
1 = 1.5 Stop Bits if 5 data bits selected,
2 Stop Bits if 6, 7, or 8 data bits
selected.
3
Parity
Enable
0 = Parity Disabled
1 = Parity Enabled
A parity bit is generated and checked
for between the last data word bit and
the stop bit.
4
Even-Parity
Select
0 = Odd Parity
1 = Even Parity
5
Stick Parity
0 = Stick Parity Disabled
1 = Stick Parity Enabled
When parity is enabled, stick parity
causes the transmission and reception
of a parity bit to be in the opposite state
from the value selected via bit 4. This
is used as a diagnostic tool to force
parity to a known state and allow the
receiver to check the parity bit in a
known state.
6
Break
Control
0 = Break Disabled
1 = Break Enabled
When break is enabled, the serial
output line (TxD) is forced to the space
state (low). This bit acts only on the
serial output and does not affect
transmitter logic. For example, if the
following sequence is used, no invalid
characters are transmitted due to the
presence of the break.
1. Load a zero byte in response to the
Transmitter Holding Register Empty
(THRE) status indication.
2. Set the break in response to the
next THRE status indication.
3. Wait for the transmitter to become
idle when the Transmitter Empty
status signal is set high (TEMT=1);
then clear the break when normal
transmission has to be restored.
7
Divisor
Latch
Access Bit
0 = Access Receiver Buffer
1 = Allow Access to Divisor Latches
Note that bit 7 must be set high to access the divisor latch registers
of the baud rate generator (DLL & DLM) during a read/write operation.
Note that writing “BF” to this register allows access to the enhanced
register functionality of IP511-64 models. Bit 7 must be low to access
the Receiver Buffer register (RBR), the Transmitter Holding Register
(THR), or the Interrupt-Enable Register (IER). A power-up or system
reset sets all LCR bits to 0.
A detailed discussion of word length, stop bits, parity, and the break
signal is included in Section 4.0 (Theory of Operation).
