SERIES IP511 INDUSTRIAL I/O PACK ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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XON/XOFF-1,2 Registers, Ports A-D (R/W)
(Model IP511-64 Only)
These registers hold the programmed XON and XOFF characters
for software flow control. XON or XOFF characters may be 1 or 2 bytes
long. The UART compares incoming data to these values and restarts
(XON) or suspends (XOFF) data transmission when a match is
detected. Note that access to these registers are granted only after
writing “BF” to the Line Control Register (LCR). All XON/XOFF bits are
set to 0 upon power-up or system reset. Refer to “Software Flow
Control” later in this section for more information.
IER - Interrupt Enable Register, Ports A-D (R/W)
The Interrupt Enable Register is used to independently enable/
disable the four possible serial channel interrupt sources that drive the
INTREQ0* line (Ports A-D share this line). Interrupts are disabled by
resetting the corresponding IER bit low (0), and enabled by setting the
IER bit high (1). Disabling the interrupt system (IER bits 0-3 low) also
inhibits the Interrupt Identification Register (IIR) and the interrupt
request line (INTREQ0*). All other functions operate in their normal
manner, including the setting of the Line Status Register (LSR) and the
Modem Status Register (MSR).
Interrupt Enable Register
IER BIT
INTERRUPT ACTION
0
Received Data Available Interrupt Enable and
Time-Out Interrupt (FIFO Mode) Enable
1
Transmitter Holding Register Empty Interrupt Enable
2
Receiver Line Status Interrupt Enable
3
Modem Status Interrupt Enable (No Function for IP511)
4-7
Not Used on IP511-16 models - Set to Logic 0
MODELS IP511-64 ONLY
4
0 = Disable Sleep Mode.
1 = Enable Sleep Mode - The UART will enter a “sleep”
power-down mode and the clock/oscillator circuit is
disabled. Any change of state on Rx, RI, CTS, DSR,
and DCD will wake-up the UART (note that none of the
handshake lines are implemented on this model). The
UART will not lose the programmed bits when sleep
mode is activated or deactivated. The UART will not
enter sleep mode if any interrupt is pending.
5
0 = Disable the Received XOFF interrupt.
1 = Enable the Received XOFF interrupt. The UART
issues an interrupt when XOFF characters are received
and correctly matched against the pre-programmed
XOFF-1,2 words.
6
NO FUNCTION FOR MODEL IP511
0 = Disable the RTS* interrupt
1 = Enable the generation of an RTS* interrupt when
RTS* changes from a low to high state. The IP511
does not implement the RTS* line and this bit should be
programmed to 0.
7
NO FUNCTION FOR MODEL IP511
0 = Disable the CTS interrupt
1 = Enable the generation of the CTS interrupt when
CTS changes from a low to high state. The IP511 does
not implement the CTS* line and this bit should be
programmed to 0.
Shaded Entries apply to Model IP511-64 functionality only.
Note that bit 3 will have no effect for the IP511 since no signal
paths are provided for any of the handshake lines (modem status lines).
A power-up or system reset sets all IER bits to 0.
Program access to the enhanced functionality provided via bits 4-7 of
this register is gained through setting EFR bit 4. For IP511-64 models,
programmed values for bits 4-7 cannot be overwritten via existing
software if EFR bit 4 is clear (these values are latched when EFR bit 4
is cleared).
IIR - Interrupt Identification Register, Ports A-D (READ Only)
The Interrupt Identification Register (IIR) is used to indicate that a
prioritized interrupt is pending and the type of interrupt that is pending.
This register will indicate the highest-priority type of interrupt pending
for the channel. Individual serial channels prioritize their interrupts into
four levels (IP511-16 models), or six levels (IP511-64 models) as
indicated below. This helps minimize software overhead during data
character transfers. Additionally, with respect to the four channels
sharing interrupt request line 0 (IntReq0), interrupts are served
according to a shifting priority scheme that is a function of the last
interrupting port served.
PRTY/LVL
INTERRUPT
1
Receiver Line Status
2
Received Data Ready or Character Time-out
3
Transmitter Holding Register Empty
4
Modem Status (No function for IP511)
5
Software Flow Control Interrupt
6
CTS/RTS Change-of-State (No function for IP511)
Shaded entries apply to IP511-64 models only.
Note that a priority level 4 or 6 interrupt will never occur for the
IP511 since no handshake signal paths (modem status lines) are
provided. The four low order bits of this register are used to identify the
interrupt pending (all units) as shown below. Bits 4 & 5 are used to
identify the additional interrupts possible for IP511-64 models.
Interrupt Identification Register
BITS
3-0
INT
PRTY
INTERRUPT
TYPE
INTERRUPT
SOURCE
RESET
CONTROL
0001
--
None
None
--
0110
1st
Receiver Line
Status
OE, PE, FE,
or BI (See
LSR Bits 1-4)
LSR Read
0100
2nd
Received
Data
Available
Receiver Data
Available or
Trigger Level
Reached
RBR Read
till FIFO
below
trigger level
1100
2nd
Character
Time-out
Indication
No characters
have been re-
moved from or
input to the Rx
FIFO during
last 4
character
times and
there is at
least 1
character in it
during this
time
RBR Read
0010
3rd
THRE (LSR
Bit 5)
THRE
(LSR Bit 5)
IIR Read (if
LSR bit 5 is
the interrupt
source) or a
THR Write
0000
4th
Modem
Status
CTS* asserted
(NOT USED)
MSR Read
