SERIES IP511 INDUSTRIAL I/O PACK ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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In the loopback diagnostic mode, transmitted data is immediately
received permitting the host processor to verify the transmit and receive
data paths of the selected serial channel. Further, modem status
interrupt generation can be controlled manually in loopback mode by
controlling the state of the four lower order MCR bits internally, instead
of by external hardware paths (these handshake lines are not used for
this model). However, in loopback mode, no interrupt requests or
interrupt vectors will actually be served, the UART only reflects that an
interrupt is pending.
Interrupt Generation
This model provides individual control for generation of transmit,
receive, line status, and data set interrupts on each of four channels.
Each channel shares interrupt request line 0 (Intreq0) according to a
unique priority shifting scheme that prevents the continuous interrupts
of one channel from freezing out other channels’ interrupt requests.
After pulling the IntReq0 line low and in response to an Interrupt
Select cycle, the current highest priority interrupt channel will serve up
its interrupt vector first. Interrupt serving priority will shift as a function
of the last port served. A unique interrupt vector may be assigned to
each communication port and is loaded into the Scratchpad Register
(SCR) for the port. The IP module will thus execute a read of the
Scratchpad Register in response to an interrupt select cycle. Two wait
states are required to complete this cycle.
Interrupt priority is assigned as follows. Initially, with no prior
interrupt history, Port A has the highest priority and will be served first,
followed by port B, followed by port C, then followed by port D.
However, if port A was the last interrupt serviced, then port B will have
the highest priority, followed by port C, followed by port D, then port A,
in a last-serviced last-out fashion. Priority continues to shift in the same
fashion if port B or port C was the last interrupt serviced. This is useful
in preventing continuous interrupts on one channel from freezing out
interrupt service for other channels.
Software Flow Control (Model IP511-64 Only)
Model IP511-64 modules includes support for software flow control.
Software flow control utilizes special XON & XOFF characters to control
the flow of data, for more efficient data transfer and to minimize overrun
errors.
Software flow control (sometimes called XON/XOFF pacing) sends
a signal from one node to another by adding flow control characters to
the data stream. The receiving node will detect the XON or XOFF
character and respond by suspending transmission of data (XOFF
turns the data flow off), or resuming transmission of data (XON turns
the data flow on). Flow control is used frequently in data
communications to prevent overrun errors or the loss of excess data.
For example, a node might transmit the XOFF character to the host
computer if the host is sending data too quickly to be processed or
buffered, thus preventing the loss of excess data.
The flow control characters are stored in the XON-1,2 and XOFF-
1,2 registers. Two XON & XOFF registers are provided because the
flow control character may be 1 or 2 bytes long. The contents of the
XON-1,2 and XOFF-1,2 registers are reset to “0” upon power-up or
system reset, and may be programmed to any value for software flow
control. Different conditions may be set to detect the XON/XOFF
characters or start/stop the transmission.
When software flow control is enabled, the UART of this model will
compare two sequential received data bytes with preprogrammed
XOFF-1,2 characters. When an XOFF match is detected, the UART
will halt transmission after completing the transmission of the current
character. The receive ready flag of the Interrupt Identification register
will be set (IIR bit 4 is set to “1” when the XOFF character has been
detected), only if enabled via bit 5 of the Interrupt Enable register (IER
bit 5 is used to enable the received XOFF interrupt). An interrupt will
then be generated. After recognition of the XOFF characters, the
UART will compare the next two incoming characters with the
preprogrammed XON-1,2 characters. If a match is detected, the UART
will resume transmission and clear the received XOFF interrupt flag
(Interrupt Identification Register bit 4). After more data has been
received, the UART will automatically send XOFF-1,2 characters as
soon as the received data passes the programmed FIFO trigger level,
causing the host to suspend transmission. The UART will then
transmit the programmed XON-1,2 characters as soon as the received
data reaches the next lowest trigger level, thus causing the host to
resume transmission (received data trigger levels are 8, 16, 56, and
60).
When single XON/XOFF characters are selected, the UART
compares the received data to these values and controls the
transmission accordingly (XON=restart transmission, XOFF=suspend
transmission). These characters are not stacked in the data buffer or
FIFO. When the
ANY
XON function is enabled (MCR bit 5 is set), the
UART will automatically resume transmission after receiving
ANY
character after having recognized XOFF and suspended transmission.
Note that the UART will automatically transmit the XON character(s)
after the flow control function is disabled, if the XOFF character(s) had
been sent prior to disabling the software flow control function. Special
cases are provided to detect the special character and stack it into the
data buffer or FIFO and these conditions are configured via bits 0-3 of
the Enhanced Feature Register (EFR).
Programming Example
The following example will demonstrate data transfer between one
channel of the host IP511-16 and another node. Both nodes will use
the FIFO mode of operation with a FIFO threshold set at 14 bytes. The
data format will use 8-bit characters, odd-parity, and 1 stop bit. Please
refer to Table 3.1 for address locations. The “H” following data below
refers to the Hexadecimal data format.
1. Write 80H to the Line Control Register (LCR).
This sets the Divisor Latch Access bit to permit access to the two
divisor latch bytes used to set the baud rate. These bytes share
addresses with the Receive and Transmit buffers, and the Interrupt
Enable Register (IER).
