SERIES IP511 INDUSTRIAL I/O PACK ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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2. Write 00H to the Divisor Latch MSB (DLM). Write 34H to the
Divisor Latch LSB (DLL).
This sets the divisor to 52 for 9600 baud (i.e. 9600 = 8MHz
÷
[16*52] ).
3. Write 0BH to the Line Control Register (LCR).
This first turns off the Divisor Latch Access bit to cause accesses
to the Receiver and Transmit buffers and the Interrupt Enable
Register. It also sets the word length to 8 bits, the number of stop
bits to one, and enables odd-parity.
4. (OPTIONAL) Write xxH to the Scratch Pad Register.
This has no effect on the operation, but is suggested to illustrate
that this register can be used as a 1-byte memory cell. Alternately,
the interrupt vector for the port may be written to this register and a
read will be performed on this register in response to an interrupt
select cycle.
5. Write 07H to the Interrupt Enable Register (IER).
This enables the receiver line status interrupts. Support for the
modem status interrupt is not available since no handshake lines
are present for this model. The line status interrupt is used to
signal unexpected error cases, such as parity or overrun errors.
The received data available and transmit holding buffer empty
interrupts have also been enabled to aid control by the host CPU in
moving data back and forth.
6. Write C7H to the FIFO Control Register (FCR).
This enables and initializes the transmit and receive FIFO’s, and
sets the trigger level of the receive FIFO interrupt to 14 bytes.
7. Read C1H from the Interrupt Identification Register (IIR).
This is done to check that the device has been programmed
correctly. The upper nibble “C” indicates that the FIFO’s have been
enabled and the lower nibble “1” indicates that no interrupts are
pending.
8. The host CPU may begin loading data into the transmit buffer by
writing data repeatedly to the Transmitter Holding Register.
This loads the transmit FIFO and initiates transmission of serial
data by the transceiver. The first serial byte will take about 100us
to transmit, so it is likely that the transmit FIFO will fill before the
first byte has actually been sent.
Depending on the protocol, the receiving side may have to
acknowledge receipt of the data stream before more data may be
sent. In this case, the host CPU would have to pause sending data
and wait for an acknowledgement on the receiving side that data
had been received properly.
9. Assuming that data has also been received, read data repeatedly
from the Receiver Buffer Register.
After 14 bytes have been received (or fewer bytes with a timeout),
an interrupt will be generated if the host CPU has not already
unloaded the receive FIFO.
4.0 THEORY OF OPERATION
This section contains information regarding the EIA/TIA-422B
serial data interface. A description of the basic functionality of the
circuitry used on the board is also included. Refer to the Block Diagram
(Drawing 4501-583), Interface Diagram (Drawing 4501-581), and
Interface Level Diagram (Drawing 4501-584), as you review this
material.
EIA/TIA-422B SERIAL INTERFACE
To understand the application of this particular interface as
opposed to the EIA-485 interface of the IP512, you must first
understand what is meant by the terms half-duplex and full-duplex.
Duplex refers to the way information is exchanged on a transmission
line and the number of lines used.
Full-duplex
means that data can be
sent in both directions at the same time, like a two-lane highway with
cars moving in each direction at the same time. However,
half-duplex
means that data can only be sent in one direction at a time, like a single
lane road where cars must take turns going in opposite directions. The
Model IP511 implements full-duplex EIA/TIA-422B using separate line
pairs for transmit and receive.
The Electronic Industries Association (EIA) in conjunction with the
Telecommunication Industries Association (TIA) introduced TIA/EIA-
422B as a balanced (differential) serial data transmission interface
standard between Data Terminal Equipment (DTE) and Data
Communication Equipment (DCE). By definition, DTE is commonly
used to represent the data source, data sink, or both. DCE is used to
represent the devices used to establish, maintain, and terminate a
connection, and to code/decode the signals between the DTE and the
transmission channel. Most computers are considered DTE devices,
while modems are DCE devices.
The EIA/TIA-422B interface is the second revision of this standard
and specifies the interconnection of a balanced driver with multiple
balanced receivers. Balanced data transmission refers to the fact that
two conductors are switched per signal and the logical state of the data
is referenced by the difference in potential between the two conductors,
not with respect to signal ground. The differential method of data
transmission makes EIA-422B ideal for noisy environments since it
minimizes the effects of coupled noise and ground potential differences.
That is, since these effects are seen as common-mode voltages
(common to both lines), not differential, they are rejected by the
receivers. Additionally, balanced drivers have faster transition times
and allow operation at higher data rates over longer distances. The
EIA/TIA-422B standard defines a unidirectional, terminated, single
driver and multiple receiver configuration. By providing a separate data
path for transmit and receive, full-duplex operation is accomplished.
The maximum data transmission cable length is generally limited to
4000 feet without a signal repeater installed.
EIA/TIA-422B is electrically similar to EIA-485, except that EIA-485
supports multiple driver operation (multiple networked drivers and
receivers sharing the same data path). Consequently, this board may
be used to implement a full-duplex EIA-485 interface (see Drawing
4501-581). However, for true half-duplex EIA-485 operation, please
see the Acromag Models IP502 & IP512.
