Acromag IP511 Series User Manual Download Page 21

SERIES IP511 INDUSTRIAL I/O PACK                ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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6.0  SPECIFICATIONS

GENERAL SPECIFICATIONS

UART...........................................Texas Instruments TL16C554FN
                                                      or equivalent (Model IP511-16).
                                                      Startech ST16C654CJ68 (Model
                                                      IP511-64).  UART’s are pin-for-
                                                      pin compatible, but the Startech
                                                      version includes enhanced
                                                      functionality, such as: larger
                                                      FIFO’s and software flow controls.
Operating Temperature.................0 to +70

°

C.

Relative Humidity..........................5-95% non-condensing.
Storage Temperature....................-40

°

C to +125

°

C.

Physical Configuration..................Single Industrial I/O Pack Module.

Length....................................3.880 inches (98.5 mm).
Width.....................................1.780 inches (45.2 mm).
Board Thickness....................0.062 inches (1.59 mm).
Max Component Height..........0.314 inches (7.97 mm).

Connectors:

P1 (IP Logic Interface)............50-pin female receptacle header
                                               (AMP 173279-3 or equivalent).
P2 (Field I/O)..........................50-pin female receptacle header
                                               (AMP 173279-3 or equivalent).

Power:

+5 Volts (

±

5%).......................110mA Typical, 160mA Maximum

                                               in isolated mode with ports
                                               powered externally.  130mA
                                               Typical, 220mA Maximum, in non-
                                               isolated mode with port power
                                               jumpers present and sharing
                                               the logic supply.

±

12 Volts (

±

5%) from P1.......0mA (Not Used).

Isolation........................................Port-to-Logic - Logic and field lines

                                               are isolated from each other for
                                               voltages up to 250VAC, or 354V
                                               DC on a continuous basis when
                                               ports are powered externally with
                                               isolated supplies (will withstand
                                               1000V AC dielectric strength test
                                               for one minute without break-
                                               down).  Note that port power and
                                               common may be jumpered to
                                               share logic power for non-isolated
                                               operation.  These ratings apply in
                                               isolated mode with power jumpers
                                               removed.

Isolation Spacing..........................Minimum printed circuit board

                                               isolation spacings are as follows:
                                               Port-to-Logic - 0.023” Minimum;
                                               Port-to-Port - 0.022” Minimum.
                                               These spacings apply to inner
                                               layer foil spacings (outer layer
                                               clearances are greater).

Resistance to RFI.........................No data upsets occur for field
                                                     strengths up to 10V per meter at
                                                     27MHz, 151MHz, & 460MHz per
                                                     SAMA PMC 33.1 test procedures.
Resistance to EMI........................Unit has been tested with no
                                                     data upsets under the influence
                                                     of EMI from switching solenoids,
                                                     commutator motors, and drill
                                                     motors.

Surge Withstand Capability..........Interface lines exhibit no damage
                                                     when tested with a waveform
                                                     representative of surges (high
                                                     frequency transient electrical
                                                     interference) to 

±

1KV in isolated

                                                     mode.
ESD Protection.............................EIA/TIA-422B lines are protected
                                                     from ESD voltages to 

 

±

2KV in

                                                     isolated mode.

EIA/TIA-422B PORTS

Configuration.................................Four independent, isolated,
                                                      full-duplex, EIA/TIA-422B serial
                                                      ports with separate signal
                                                      common and +5V input power
                                                      connections.
Transceiver...................................Linear Technology LTC490CS8
                                                      or equivalent.  Designed for
                                                      EIA/TIA-422B or EIA-485.
Port Power Requirements.............Is5V (+4.75V to +5.25V),
                                                      15mA maximum, each port.
                                                      Note: If non-isolated operation is
                                                      desired, the port power and
                                                      ground jumpers may be
                                                      programmed to provide port power
                                                      from the +5V logic supply
                                                      provided by the carrier board (see
                                                      Drawing 4501-582).
Data Rate......................................Programmable to 512K bits/sec
                                                      using internal baud rate generator.
Interface........................................Asynchronous serial only.
Maximum Cable Length................1200M (4000 feet) typical.  Use of
                                                      a signal repeater can extend
                                                      transmission distances beyond
                                                      this limit.
Character Size..............................Software programmable 5-8 bits.
Parity............................................Software programmable odd, even,
                                                      or no parity.
Stop Bits.......................................Software programmable 1, 1-1/2,
                                                      or 2 bits.
Data Register Buffers...................The data registers are double-
                                                      buffered (16C450 mode), or 16-
                                                      byte FIFO buffered (standard unit,
                                                      FIFO mode), or 64-byte FIFO
                                                      buffered (IP511-64 models).
Interrupts.......................................Receiver Line Status Interrupt (i.e.
                                                      Overrun error, Parity error,
                                                      Framing error, or Break Interrupt);
                                                      Received Data Available (FIFO
                                                      level reached) or Character Time-
                                                      Out; Transmitter Holding Register
                                                      Empty.  IP511-64 units include
                                                      interrupts for received XOFF
                                                      signal/special character.  Multiple
                                                      port Interrupts share the IntReq0
                                                      line according to a shifting-priority
                                                      scheme based on the last
                                                      interrupting port serviced.

Summary of Contents for IP511 Series

Page 1: ...tion Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1996 Acromag Inc Printed in the USA Data and spe...

Page 2: ...ystem This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acr...

Page 3: ...er Acromag IP modules are also available to serve your signal conditioning and interface needs Note Since all connections to field signals are made through the carrier board which passes them to the i...

Page 4: ...ive data paths This SIP can be easily removed or replaced if required see Drawing 4501 581 4501 582 Network Termination Bias Resistor Placement You need to consider your network application carefully...

Page 5: ...h To the communication network master this line pair is used as the transmit data path To the communication network slave this line pair comprises the receive data path Because a separate pair of line...

Page 6: ...ides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environ...

Page 7: ...Port A Line Control Register 07 08 Not Driven1 R W MCR Port A Modem Control Register 09 0A Not Driven1 R W LSR Port A Line Status Register 0B 0C Not Driven1 R W MSR Port A Modem Status Register 0D 0E...

Page 8: ...R W SCR Port C Scratch Pad Interrupt Vector Register 2F Shaded register entries apply to Model IP511 64 only and are accessible after writing BF to the Line Control Register LCR Table 3 1 IP511 I O Sp...

Page 9: ...g an invalid data character due to a low going noise spike on RxD If the data on RxD is a symmetrical square wave the center of the data cells will occur within 3 125 of the actual center providing an...

Page 10: ...extended register functionality of IER bits 4 7 IIR bits 4 5 FCR bits 4 5 and MCR bits 5 7 It is also used to program software flow control Note that bits 6 7 are used for hardware flow control but th...

Page 11: ...7 NO FUNCTION FOR MODEL IP511 0 Disable the CTS interrupt 1 Enable the generation of the CTS interrupt when CTS changes from a low to high state The IP511 does not implement the CTS line and this bit...

Page 12: ...FO TRIGGER LEVEL 00 01 Bytes 08 Bytes for IP511 64 Models 01 04 Bytes 16 Bytes for IP511 64 Models 10 08 Bytes 56 Bytes for IP511 64 Models 11 14 Bytes 60 Bytes for IP511 64 Models LCR Line Control Re...

Page 13: ...the selected serial channel In Loopback Mode interrupts are generated by controlling the state of the four lower order MCR bits internally instead of by the external hardware paths However no interru...

Page 14: ...errupt a priority 1 interrupt in the IIR register when any one of these conditions are detected This interrupt is enabled by setting IER bit 2 to 1 A power up or system reset sets all LSR bits to 0 ex...

Page 15: ...Low Interrupt Modem Status Changes Read MSR Reset Low OUT1 Reset High OUT2 Reset High After a power up the isolation buffer s output is initialized high As a result the very first bit transmitted or...

Page 16: ...the FIFO drops below its trigger level When the receiver FIFO and receiver interrupts are enabled the following receiver FIFO character time out status conditions apply 1 A FIFO character time out int...

Page 17: ...oo quickly to be processed or buffered thus preventing the loss of excess data The flow control characters are stored in the XON 1 2 and XOFF 1 2 registers Two XON XOFF registers are provided because...

Page 18: ...functionality of the circuitry used on the board is also included Refer to the Block Diagram Drawing 4501 583 Interface Diagram Drawing 4501 581 and Interface Level Diagram Drawing 4501 584 as you re...

Page 19: ...nsmit the byte Two other parity formats not supported by this module are mark parity and space parity Mark parity specifies that the parity bit will always be a logical 1 space parity requires the par...

Page 20: ...ed isolated only when isolated external port power is provided to the port Optionally the port may use P1 power by programming the power and common jumpers appropriately In this mode the port is consi...

Page 21: ...o RFI No data upsets occur for field strengths up to 10V per meter at 27MHz 151MHz 460MHz per SAMA PMC 33 1 test procedures Resistance to EMI Unit has been tested with no data upsets under the influen...

Page 22: ...performance with precision analog I O applications Application Used to connect a Model 5025 552 termination panel to the AVME9630 9660 non intelligent carrier board A D connectors both have 50 pin con...

Page 23: ...r Boards Application This panel converts the high density ribbon cable connectors coming from the APC8600 carrier board Acromag cable Model 5029 900 to screw terminals for direct wired interfaces This...

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