SERIES IP511 INDUSTRIAL I/O PACK ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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Table 3.2: IP511 ID Space Identification (ID) PROM
Hex Offset
From ID
PROM Base
Address
ASCII
Character
Equivalent
Numeric
Value
(Hex)
Field Description
01
I
49
All IP's have 'IPAC'
03
P
50
05
A
41
07
C
43
09
A3
Acromag ID Code
0B
14
IP Model Code
1
0D
00
Not Used
(Revision)
0F
00
Reserved
11
00
Not Used (Driver
ID Low Byte)
13
00
Not Used (Driver
ID High Byte)
15
0C
Total Number of ID
PROM Bytes
17
FD
CRC
19 to 3F
yy
Not Used
Notes (Table 3.2):
1. The IP model number is represented by a two-digit code within the
ID PROM (the IP511 model is represented by 14 Hex).
THE EFFECT OF RESET
A software or hardware reset puts the serial channels into an idle-
mode until initialization (programming). A reset initializes the receiver
and transmitter clock counters. It also clears the Line-Status Register
(LSR), except for the transmitter shift-register empty (TEMT) and
transmit holding-register empty (THRE) bits which are set to 1 (note
that when interrupts are subsequently enabled, an interrupt will occur
due to THRE being set). All of the discrete signal lines, memory
elements, and miscellaneous logic associated with these register bits
are cleared, de-asserted, or turned off. However, the Line Control
Register (LCR), divisor latches, Receiver Buffer Register (RBR), and
Transmitter Holding Register (THR) are not affected. The following
table summarizes the effect of a reset on the various registers and
internal and external signals:
The Effect of Reset:
REGISTER/
SIGNAL
RESET
CONTROL
STATE/EFFECT
REGISTERS:
IER
Reset
All Bits low.
IIR
Reset
Bit 0 high, Bits 1-7 low.
LCR
Reset
All bits low.
MCR
Reset
All bits low.
FCR
Reset
All bits low.
LSR
Reset
All bits low, except bits 5 & 6
which are high.
MSR
Reset
Bits 0-3 low, bits 4-7 per
corresponding input signal.
EFR
Reset
All bits low.
XON-1,2
Reset
All bits low.
XOFF-1,2
Reset
All bits low.
The Effect of Reset...continued:
REGISTER/
SIGNAL
RESET
CONTROL
STATE/EFFECT
SIGNALS (INTERNAL & EXTERNAL):
TxD
Reset
High
Interrupt (RCVR
errors)
Read LSR/
Reset
Low
Interrupt (RCVR
data ready)
Read RCVR
Buffer
Register/
Reset
Low
Interrupt
(THRE)
Read
IIR/Write
THR/Reset
Low
Interrupt
(Modem Status
Changes)
Read MSR/
Reset
Low
OUT1*
Reset
High
OUT2*
Reset
High
After a power-up, the isolation buffer’s output is initialized “high”.
As a result, the very first bit transmitted or received along the TxD or
RxD paths after power-up may be a “1”. If the first bit happens to be a
“0”, it could be converted to a “1”, and a data error may be reported.
However, subsequent changes in the driving data at the input-side of
the isolation buffer will be correctly reflected across the isolation barrier.
This is a potential drawback of this particular isolation scheme. Keep
this in mind if a data error occurs for the first bit of the first byte
received or transmitted after power-up.
IP511 PROGRAMMING
Each serial channel of this module is programmed by the control
registers: LCR, IER, DLL, DLM, MCR, and FCR. Since none of the
UART handshake lines are supported by this model, not all of the
available register status and controls are functional. However, control
words are available to define the character length, number of stop bits,
parity, baud rate, interrupts, and transceiver mode (receive or transmit).
The control registers can be written in any order, but the IER register
should be written last since it controls the interrupt enables. The
contents of these registers may be updated any time the serial channel
is not transmitting or receiving data.
The complete status of each channel can be read by the host CPU
at any time during operation. Normally, two registers are used to report
the status of a particular channel: the Line Status Register (LSR) and
the Modem Status Register (MSR). However, since this model
provides no handshake support, the Modem Status Register has no
function.
Serial channel data is read from the Receiver Buffer Register
(RBR), and written to the Transmitter Holding Register (THR). Writing
data to the THR initiates the parallel-to-serial transmitter shift register to
the TxD line. Likewise, input data is shifted from the RxD pin to the
Receiver Buffer Register. The Scratchpad Register is used to store
the interrupt vector for the port. In response to an interrupt select cycle,
the IP module will provide a read of this port. As such, each port may
have a unique interrupt vector assigned. Interrupts are served in a
shifting-priority fashion that is a function of the last interrupting port
serviced. This prevents continuous interrupts from one channel from
freezing out service of another interrupting channel.
