Acromag IP511 Series User Manual Download Page 2

SERIES IP511 INDUSTRIAL I/O PACK                ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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The information contained in this manual is subject to change without
notice.  Acromag, Inc. makes no warranty of any kind with regard to this
material, including, but not limited to, the implied warranties of
merchantability and fitness for a particular purpose.  Further, Acromag,
Inc. assumes no responsibility for any errors that may appear in this
manual and makes no commitment to update, or keep current, the
information contained in this manual.  No part of this manual may be
copied or reproduced in any form, without the prior written consent of
Acromag, Inc.

Table of Contents

      Page

1.0   GENERAL INFORMATION

...............................................

2

        KEY IP511 FEATURES.....................................................

2

        SIGNAL INTERFACE PRODUCTS..................................

3

        INDUSTRIAL I/O PACK SOFTWARE LIBRARY..............

3

2.0   PREPARATION FOR USE

................................................

4

        UNPACKING AND INSPECTION.....................................

4

        CARD CAGE CONSIDERATIONS...................................

4

        BOARD CONFIGURATION..............................................

4

            Network Termination & Bias Resistor Placement...........

4

            Power Jumper Configuration..........................................

4

        CONNECTORS.................................................................

4

            IP Field I/O Connector (P2)............................................

4

            Noise and Grounding Considerations.............................

5

            IP Logic Interface Connector (P1)..................................

6

3.0

   

PROGRAMMING INFORMATION

....................................

6

        ADDRESS MAPS..............................................................

6

            IP Communication & Configuration Registers................

9

            IP Identification PROM...................................................

14

        THE EFFECT OF RESET.................................................

15

        IP511 PROGRAMMING....................................................

15

            FIFO Polled Mode..........................................................

16

            FIFO Interrupt Mode.......................................................

16

            Loopback Mode Operation.............................................

16

            Interrupt Generation.......................................................

17

            Software Flow Control....................................................

17

            Programming Example...................................................

17

4.0

   

THEORY OF OPERATION

...............................................

18

        EIA/TIA-422B SERIAL INTERFACE.................................

18

        IP511 OPERATION...........................................................

20

        LOGIC/POWER INTERFACE...........................................

20

5.0 

  

SERVICE AND REPAIR

....................................................

20

        SERVICE AND REPAIR ASSISTANCE...........................

20

        PRELIMINARY SERVICE PROCEDURE.........................

20

6.0

   

SPECIFICATIONS

.............................................................

21

        GENERAL SPECIFICATIONS..........................................

21

        EIA/TIA-422B PORTS.......................................................

21

        INDUSTRIAL I/O PACK COMPLIANCE...........................

22

        

APPENDIX

.........................................................................

22

        CABLE: MODEL 5025-550. & 5025-551...........................

22

        CABLE: MODEL 5029-943................................................

22

        CABLE: MODEL 5029-900................................................

22

        TERMINATION PANEL: MODEL 5025-552.....................

23

        TERMINATION PANEL: MODEL 5029-910.....................

23

        TRANSITION MODULE: MODEL TRANS-GP.................

23

        

DRAWINGS

Page

        4501-434  IP MECHANICAL ASSEMBLY.........................

24

        4501-580  IP511 COMMUNICATION CONNECTIONS...

24

        4501-581  IP511 INTERFACE DIAGRAM........................

25

        4501-582  IP511 TERM RES & JUMPER LOCATION.....

26

        4501-583  IP511 BLOCK DIAGRAM.................................

27

        4501-584  RS-422 INTERFACE LEVELS.........................

28

        4501-462  CABLE 5025-550 (NON-SHIELDED)..............

29

        4501-463  CABLE 5025-551 (SHIELDED)........................

29

        4501-464  TERMINATION PANEL 5025-552...................

30

        4501-465  TRANSITION MODULE TRANS-GP...............

30

                  IMPORTANT SAFETY CONSIDERATIONS

 It is very important for the user to consider the possible adverse
 effects of power, wiring, component, sensor, or software failures in
 designing any type of control or monitoring system.  This is
 especially important where economic property loss or human life is
 involved.  It is important that the user employ satisfactory overall
 system design.  It is agreed between the Buyer and Acromag, that
 this is the Buyer's responsibility.

1.0   GENERAL INFORMATION

The Industrial I/O Pack (IP) Series IP511 module provides four

isolated EIA/TIA-422B serial communication ports for interfacing to the
VMEbus or ISAbus, according to your carrier board.  This module
implements full-duplex EIA/TIA-422B and includes four isolated data
paths for Transmit and Receive (Tx

±

 & Rx

±

).  Four units may be

mounted on a carrier board to provide up to 16 asynchronous serial
ports per system slot.  For non-isolated requirements, refer to Acromag
Model IP501 (the non-isolated companion to this model).

The transmit and receive paths of each channel on IP511-16 units

include generous 16-byte FIFO buffers to minimize CPU interaction.
Model IP511-64 units utilize 64-byte FIFO buffers and include software
flow controls.  Character size, stop bits, parity, and baud rate are
software configurable.  Prioritized interrupt generation is also supported
for transmit, receive, line-status, and data set conditions.  The IP511
utilizes state of the art Surface-Mounted Technology (SMT) to achieve
its wide functionality, and is an ideal choice for a wide range of
industrial communication interface applications that require a highly
reliable, high-performance interface at a low cost.

KEY IP511 FEATURES

 

High Density

 - Provides programmable control of four isolated

EIA/TIA-422B serial I/O ports.  Four units mounted on a carrier
board provide 16 serial channels in a single VMEbus or ISAbus
(PC/AT) system slot.

 

High-Voltage Isolation -

 This module provides four

independently isolated serial ports protected for voltages up to
250VAC.  This module will survive a 1000VAC dielectric strength
test for 1 minute without breakdown.

 

Large FIFO Buffers - 

Both the transmit and receive channels of

each serial port provide generous 16-character (Model IP511-16),
or 64-character (Model IP511-64) data buffering (plus 3 framing
bits per character).  This gives the host CPU additional time to
process other applications and reduces CPU interactions and
interrupts.

 

Programmable Character Size -

 Each serial port is software

programmable for 5, 6, 7, or 8 bit character sizes.

 

Programmable Stop Bits -

 Each serial port allows 1, 1.5, or 2

stop-bits to be added to, or deleted from, the serial data stream.

 

Programmable Parity Generation & Detection

 - Even, Odd, or

No Parity generation and detection is supported

.

 

Line-Break Generation & Detection -

 provision for sending and

detecting the line break character is provided.

 

False Start Bit Detection - 

Prevents the receiver from

assembling false data characters due to low-going noise spikes on
the RxD input line.

Summary of Contents for IP511 Series

Page 1: ...tion Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1996 Acromag Inc Printed in the USA Data and spe...

Page 2: ...ystem This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acr...

Page 3: ...er Acromag IP modules are also available to serve your signal conditioning and interface needs Note Since all connections to field signals are made through the carrier board which passes them to the i...

Page 4: ...ive data paths This SIP can be easily removed or replaced if required see Drawing 4501 581 4501 582 Network Termination Bias Resistor Placement You need to consider your network application carefully...

Page 5: ...h To the communication network master this line pair is used as the transmit data path To the communication network slave this line pair comprises the receive data path Because a separate pair of line...

Page 6: ...ides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environ...

Page 7: ...Port A Line Control Register 07 08 Not Driven1 R W MCR Port A Modem Control Register 09 0A Not Driven1 R W LSR Port A Line Status Register 0B 0C Not Driven1 R W MSR Port A Modem Status Register 0D 0E...

Page 8: ...R W SCR Port C Scratch Pad Interrupt Vector Register 2F Shaded register entries apply to Model IP511 64 only and are accessible after writing BF to the Line Control Register LCR Table 3 1 IP511 I O Sp...

Page 9: ...g an invalid data character due to a low going noise spike on RxD If the data on RxD is a symmetrical square wave the center of the data cells will occur within 3 125 of the actual center providing an...

Page 10: ...extended register functionality of IER bits 4 7 IIR bits 4 5 FCR bits 4 5 and MCR bits 5 7 It is also used to program software flow control Note that bits 6 7 are used for hardware flow control but th...

Page 11: ...7 NO FUNCTION FOR MODEL IP511 0 Disable the CTS interrupt 1 Enable the generation of the CTS interrupt when CTS changes from a low to high state The IP511 does not implement the CTS line and this bit...

Page 12: ...FO TRIGGER LEVEL 00 01 Bytes 08 Bytes for IP511 64 Models 01 04 Bytes 16 Bytes for IP511 64 Models 10 08 Bytes 56 Bytes for IP511 64 Models 11 14 Bytes 60 Bytes for IP511 64 Models LCR Line Control Re...

Page 13: ...the selected serial channel In Loopback Mode interrupts are generated by controlling the state of the four lower order MCR bits internally instead of by the external hardware paths However no interru...

Page 14: ...errupt a priority 1 interrupt in the IIR register when any one of these conditions are detected This interrupt is enabled by setting IER bit 2 to 1 A power up or system reset sets all LSR bits to 0 ex...

Page 15: ...Low Interrupt Modem Status Changes Read MSR Reset Low OUT1 Reset High OUT2 Reset High After a power up the isolation buffer s output is initialized high As a result the very first bit transmitted or...

Page 16: ...the FIFO drops below its trigger level When the receiver FIFO and receiver interrupts are enabled the following receiver FIFO character time out status conditions apply 1 A FIFO character time out int...

Page 17: ...oo quickly to be processed or buffered thus preventing the loss of excess data The flow control characters are stored in the XON 1 2 and XOFF 1 2 registers Two XON XOFF registers are provided because...

Page 18: ...functionality of the circuitry used on the board is also included Refer to the Block Diagram Drawing 4501 583 Interface Diagram Drawing 4501 581 and Interface Level Diagram Drawing 4501 584 as you re...

Page 19: ...nsmit the byte Two other parity formats not supported by this module are mark parity and space parity Mark parity specifies that the parity bit will always be a logical 1 space parity requires the par...

Page 20: ...ed isolated only when isolated external port power is provided to the port Optionally the port may use P1 power by programming the power and common jumpers appropriately In this mode the port is consi...

Page 21: ...o RFI No data upsets occur for field strengths up to 10V per meter at 27MHz 151MHz 460MHz per SAMA PMC 33 1 test procedures Resistance to EMI Unit has been tested with no data upsets under the influen...

Page 22: ...performance with precision analog I O applications Application Used to connect a Model 5025 552 termination panel to the AVME9630 9660 non intelligent carrier board A D connectors both have 50 pin con...

Page 23: ...r Boards Application This panel converts the high density ribbon cable connectors coming from the APC8600 carrier board Acromag cable Model 5029 900 to screw terminals for direct wired interfaces This...

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