SERIES IP511 INDUSTRIAL I/O PACK ISOLATED QUAD EIA/TIA-422B COMMUNICATION MODULE
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This board operates in two different modes. In one mode, this
device remains software compatible with the industry standard 16C450
family of UART’s, and provides double-buffering of data registers. In
the FIFO Mode (enabled via bit 0 of the FCR register), data registers
are FIFO-buffered so that read and write operations can be performed
while the UART is performing serial-to-parallel and parallel-to-serial
conversions.
Two FIFO modes of operation are possible: FIFO Interrupt Mode
and FIFO Polled Mode. In FIFO Interrupt Mode, data transfer is
initiated by reaching a pre-determined trigger-level or generating time-
out conditions. In FIFO-Polled Mode, there is no time-out condition
indicated or trigger-level reached. The transmit and receive FIFO’s
simply hold characters and the Line Status Register must be read to
determine the channel status.
Acromag provides an Industrial I/O Pack Software Library diskette
(Model IPSW-LIB-M03, MSDOS format) to simplify communication with
the board. Example software functions are provided for both ISA bus
(PC/AT) and VMEbus applications. All functions are written in the “C”
programming language and can be linked to your application. For more
details, refer to the “README.TXT” file in the root directory on the
diskette and the “INFO511.TXT” file in the appropriate “IP511”
subdirectory off of “\VMEIP” or “\PCIP”, according to your carrier.
FIFO Polled-Mode
Resetting Interrupt Enable Register Bit 0, Bit 1, Bit 2, Bit 3, or all
four to 0, with FIFO Control Register (FCR) Bit 0 =1, puts the channel
into the polled-mode of operation. The receiver and transmitter are
controlled separately and either one or both may be in the polled mode.
In FIFO-Polled Mode, there is no time-out condition indicated or trigger-
level reached, the transmit and the receive FIFO’s simply hold
characters and the Line Status Register must be read to determine the
channel status.
FIFO-Interrupt Mode
In FIFO Interrupt Mode, data transfer is initiated by reaching a pre-
determined trigger-level or generating a time-out condition. Please note
the following with respect to this mode of operation.
When the receiver FIFO and receiver interrupts are enabled, the
following receiver status conditions apply:
1. LSR Bit 0 is set to 1 when a character is transferred from the shift
register to the receiver FIFO. It is reset to 0 when the FIFO is
empty.
2. The receiver line-status interrupt (IIR=06) has a higher priority than
the received data-available interrupt (IIR=04).
3. The receive data-available interrupt is issued to the CPU when the
programmed trigger level is reached by the FIFO. It is cleared
when the FIFO drops below its programmed trigger level. The
receive data-available interrupt indication (IIR=04) also occurs
when the FIFO reaches its trigger level, and is cleared when the
FIFO drops below its trigger level.
When the receiver FIFO and receiver interrupts are enabled, the
following receiver FIFO character time-out status conditions apply:
1. A FIFO character time-out interrupt occurs if:
•
A minimum of one character is in the FIFO.
•
The last received serial character occurred longer than four
continuous prior character times earlier (if 2 stop bits are
programmed, the second one is included in the time delay).
•
The last CPU read of the FIFO occurred more than four
continuous character times earlier. At 300 baud, and with 12-
bit characters, the FIFO time-out interrupt causes a latency of
160ms maximum from received character to interrupt issued.
2. From the clock signal input, the character times can be calculated.
The delay is proportional to the baud rate.
3. The time-out timer is reset after the CPU reads the receiver FIFO or
after a new character is received when there has been no time-out
interrupt.
4. A time-out interrupt is cleared and the timer is reset when the CPU
reads a character from the receiver FIFO.
When the transmit FIFO and transmit interrupts are enabled (FCR
Bit 0 = 1 and IER=01), a transmitter interrupt will occur as follows:
1. When the transmitter FIFO is empty, the transmitter holding register
interrupt (IIR=02) occurs. The interrupt is cleared when the
Transmitter Holding Register (THR) is written to or the Interrupt
Identification Register (IIR) is read. One to sixteen characters can
be written to the transmit FIFO when servicing this interrupt.
2. The transmit FIFO empty indications are delayed one character time
minus the last stop bit time when the following occurs:
Bit 5 of the LSR (THRE) is 1 and there is not a minimum of two
bytes at the same time in the transmit FIFO since the last time
THRE=1. The first transmitter interrupt after changing FCR Bit 0 is
immediate, assuming it is enabled.
The receiver FIFO trigger level and character time-out interrupts
have the same priority as the received data-available interrupt. The
Transmitter Holding-Register-Empty interrupt has the same priority as
the Transmitter FIFO-Empty interrupt.
Loopback Mode Operation
This device may be operated in a “loopback mode”, useful for
troubleshooting a serial channel without physically wiring to the channel.
Bit 4 of the Modem Control Register (MCR) is used to program the local
loopback feature for the UART channel. When set high, the UART
channel’s serial output line (Transmit Data Path) is set to the marking
(logic 1 state), and the UART receiver serial data input lines are
disconnected from the transceiver RxD path. The output of the UART
transmitter shift register is then looped back into the receiver shift
register input. Thus, a write to the Transmitter Holding Register is
automatically looped back to the corresponding Receiver Buffer
Register. Likewise, the four modem control outputs of the UART (DTR,
RTS, OUT1, and OUT2 of the MCR Register) are internally connected
to the corresponding four modem control inputs (monitored via the
Modem Status Register), while their associated pins are forced to their
high/ inactive state. However, this model does not provide signal paths
for any of the handshake lines.
