W7500x Reference Manual Version1.1.0
18 / 399
Interrupt generation logic ..................................................................... 363
Enable PrimeCell SSP operation .............................................................. 366
Programming the SSPCR0 Control Register ................................................. 367
Programming the SSPCR1 Control Register ................................................. 367
Texas Instruments synchronous serial frame format ...................................... 369
Motorola SPI frame format .................................................................... 370
National Semiconductor Microwire frame format ......................................... 376
Master and Slave configurations .............................................................. 378
SSP0 Registers (Base Address : 0x4000_A000) ........................................ 380
SSP0 Control register 0 (SSP0CR0) ........................................................... 380
SSP0 Control register 1 (SSP0CR1) ........................................................... 382
SSP0 Data register (SSP0DR)................................................................... 382
SSP0 Status register (SSP0SR) ................................................................. 383
SSP0 Clock prescale register (SSP0CPSR) ................................................... 384
SSP0 Interrupt mask set or clear register (SSP0IMSC) .................................... 384
SSP0 Raw interrupt status register (SSP0RIS) .............................................. 385
SSP0 Masked interrupt status register, (SSP0MIS).......................................... 385
SSP0 Interrupt clear register (SSP0ICR) ..................................................... 386
SSP0 DMA control register, (SSP0DMACR) ................................................... 386
Register map ............................................................................... 388
SSP1 Registers (Base Address : 0x4000_B000) ........................................ 389
SSP1 Control register 0 (SSP1CR0) ........................................................... 389
SSP1 Control register 1 (SSP1CR1) ........................................................... 390
SSP1 Data register (SSP1DR)................................................................... 392
SSP1 Status register (SSP1SR) ................................................................. 392
SSP1 Clock prescale register (SSP1CPSR) ................................................... 393
SSP1 Interrupt mask set or clear register (SSP1IMSC) .................................... 393
SSP1 Raw interrupt status register (SSP1RIS) .............................................. 394
SSP1 Masked interrupt status register, (SSP1MIS).......................................... 394
SSP1 Interrupt clear register (SSP1ICR) ..................................................... 395
SSP1 DMA control register, (SSP1DMACR) ................................................... 395
Register map ............................................................................... 397
Содержание W7500
Страница 28: ...W7500x Reference Manual Version1 1 0 28 399 Memory map Figure 2 W7500x memory map ...
Страница 324: ...W7500x Reference Manual Version1 1 0 324 399 Figure 46 UART character frame ...
Страница 391: ...W7500x Reference Manual Version1 1 0 391 399 1 SSP1 must not drive the SSPTXD output in slave mode ...