Tektronix TLA7AA1, Руководство пользователя, Страница: 31 / 173

Specifications
1- 4
TLA7AXX Logic Analyzer Module Service Manual
Table 1- 3: Channel width and depth
Characteristic Description
Number of channels
TLA7AA4, TLA7AB4 128 data, 8 clock/qualifier
TLA7AA3 96 data, 6 clock/qualifier
TLA7AA2, TLA7AB2 64 data, 4 clock/qualifier
TLA7AA1 32 data, 2 clock/qualifier
Acquisition memory depth
TLA7AAx series 32 M per channel
TLA7ABx series 64 M per channel
Table 1- 4: Clocking
Characteristic Description
Asynchronous clocking
n
Internal sampling period 500 ps to 50 ms in a 1--2--5 sequence. Storage control can be used to only store data
when it has changed (transitional storage)
2 ns minimum for all channels
1 ns minimum for half channels (using 2:1 Demultiplex mode)
0.5 ns minimum for quarter channels (using 4:1 Demultiplex mode)
n
Minimum recognizable word
1
(across all channels)
Channel-to-channel skew + sample uncertainty
Example for a P6860 high-density probe and a 2 ns sample period:
400 ps + 2 ns = 2.4 ns
Synchronous clocking
Master clock channels
2
Product Clock channels Master clock channels
2
Product Clock channels
32+2 module 2
64+4 module 4
96+6 module 4
128+8 module 4
Merged slave clock channels
2
Product Clock channels Merged slave clock channels
2
Product Clock channels g
(64+4 channel modules and 32+2 channel
d l b d )
96+6 module 4
(
modules cannot be merged.)
128+8 module 4