Chapter 7: BIOS
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SUPERSERVER 8048B-TRFT USER'S MANUAL
MMIO P2P Disable
Select No to prevent MMIO (Memory-Mapped I/0) P2P (PCI-E device to PCI-E
device) signals from crossing the CPU socket. The options are
No
and Yes.
PPIN Opt-in
Select Yes to use the Protected-Processor Inventory Number (PPIN) in the
system. The options are
No
and Yes.
Resource Auto Adjust
Select Enable for the PCI resource-requests for each CPU socket to be auto-
matically adjusted on the need-base when the PCI resource allocator fails. The
options are
Enable
and Disable.
QPI Per Socket Configuration
CPU 0/CPU 1/CPU 2/CPU 3
Bus Resource Allocation Ratio
Use this feature to set the bus resource-allocation ratio (from 0-8). The default
setting is
1
.
IO Resource Allocation Ratio
Use this feature to set the IO resource-allocation ratio (from 0-8). The default
setting is
1
.
MMIOL Resource Allocation Ratio
Use this feature to set the Memory-Mapped IO resource-allocation ratio (from
0-8). The default setting is
1
.
IIO UniPhy Disable
Select Yes to hide the entire UNIFY in L2 cache. The options are
No
, Yes, and
Yes w/Memory Hot Add.
Memory Configuration
This section displays the following Integrated Memory Controller (IMC) informa-
tion.
Promote Warnings
Select Enable to treat memory warnings as memory errors or memory faults for
system-level debugging. The options are
Enable
and Disable.
DDR Speed
Use this feature to force a DDR3 memory module to run at a frequency other
than what is specified in the specification. The options are
Auto
, 800, 1067,
1333, 1600, 1867, and 2133.
DDR Voltage Level
Select Force to 1.50V to force all DDR3 memory modules to operate at 1.50V.
Select Force to 1.35V to force all DDR3 memory modules to operate at 1.35V.
The options are
Auto
, Force to 1.50V, and Force to 1.35V.
Advanced Clk (Clock) Training
Select Enable for Advanced Clock Training support, which will allow the memory
command line to be synchronized with the clock line to enhance memory perfor-
mance. The options are
Enable
and Disable.
Perbit (Per-bit) Deskew Training
Select Enable for Perbit Deskew Training support, which will allow the memory
controller to include various adjustable delay circuits in both Read and Write
paths on a per-bit base for effective memory interface to maximize memory
performance. The options are
Disable
and Enable.
DDT Timing Mode
Use this feature to set the DDT (Distributed Debugging Tool) Timing mode for
the memory controller to enhance Graphical User Interface (GUI) support. The
options are
Aggressive Timing
and Conservative Timing.
MxB Rank Sharing Mapping
Use this feature to select the address-mapping setting for memory-rank sharing
to enhance extended multimedia platform performance. he options are
Maximum
Performance
and Maximum Margin.
DIMM Vref. (Voltage Reference) Circuit
This feature allows the user to decide how to configure the voltage reference
point (gate) for a DDR3 memory module. The options are Internal and
External
.
BIOS VMSE Reset
If this feature is set to Enable, BIOS settings pertaining to the Intel Scalable
Memory Interconnect 2 (Intel SMI 2) controller will be reset to improve system
performance. The options are Disable and
Enable
.
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