DocID018909 Rev 11
RM0090
Revision history
1726
28-Jul-2015
10
Embedded Flash memory interface
Section 3.7.5: Proprietary code readout protection
Power controller (PWR)
– Added the last sentence in Subsection: Entering low-power mode
of
– Added the bullet points about the interrupt in mode entry in
Table 24: Sleep-now entry and exit
Table 27: Stop mode entry and exit (for
STM32F405xx/07xx and STM32F415xx/17xx)
mode entry and exit (STM32F42xxx and STM32F43xxx)
– Added the last point to Mode entry, on return from ISR in
– Added the note in
Section: Entering sleep mode
General-purpose I/Os (GPIO)
– Updated OSPEED[1:0] definition of GPIOx_OSPEEDR register in
Section 8.4.3: GPIO port output speed register
(GPIOx_OSPEEDR) (x = A..I/J/K)
LCD-TFT Controller (LTDC)
– Corrected the bit field for WHSTPOS in the second bullet point in
Section 16.4.2: Layer programmable
Advanced-control timers (TIM1&TIM8)
– Added the note in
Section 17.3.20: Timer synchronization
,
– Updated ETF[3:0] description in
Section 17.4.3: TIM1&TIM8 slave
mode control register (TIMx_SMCR)
,
– Updated IC1F[3:0] description in
capture/compare mode register 1 (TIMx_CCMR1)
,
– Added the note to MMS2 bit description in
TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2)
,
– Added the note to SMS[2:0] bit description in
TIM1&TIM8 slave mode control register (TIMx_SMCR)
General-purpose timers (TIM2 to TIM5)
– Added the note in
Section 18.3.15: Timer synchronization
,
– Updated SMS[2:0] description in
Section 18.4.3: TIMx slave mode
– Added the note to MMS2 bit description in
,
– Added the note to SMS[2:0] bit description in
slave mode control register (TIMx_SMCR)
.
Table 310. Document revision history (continued)
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