Advanced-control timers (TIM1&TIM8)
RM0090
518/1731
DocID018909 Rev 11
Figure 91. Counter timing diagram, internal clock divided by 4
Figure 92. Counter timing diagram, internal clock divided by N
Figure 93. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
CK_PSC
0000
0001
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0035
0036
Counter overflow
Update event (UEV)
Timer clock = CK_CNT
Counter register
00
1F
20
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
CK_PSC
CK_PSC
00
CEN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 07
32 33 34 35 36
31
Auto-reload register
FF
36
Write a new value in TIMx_ARR